Design of low power 10GS/s 6-Bit DAC using  CMOS technology

Ramakrishna, P.; Kishore, K. Hari

doi:10.14419/ijet.v7i1.5.9151

Cited by 6 publications

(3 citation statements)

References 4 publications

(6 reference statements)

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“…Through the successive stage parallel adder circuit as shown in fig. 5, 0110 is added to the medieval sum output if result is greater than 9 [10][11][12][13].…”

Section: Methodsmentioning

confidence: 99%

Design of BCD Adder using Quantum Cellular Automata

J¹

2020

IJATCSE

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QCA is a technology which is transistor less and it is one of its kind and emerging technology. Working of QCA purely works on the principle of coulombic repulsions. Due to these coulombic repulsions of electrons in quantum dots, high speed digital circuits can be designed. When compared to existing CMOS technology, computational speed of Quantum Cellular Automata is significantly high. This paper mainly depicts the functioning and simulation results of BCD Adder which was designed using Quantum Cellular Automata. Digital Circuits with high complexity can be designed by using Quantum Cellular Automata by using crossovers. When crossovers and multi-layer connections are used area occupied by the circuit and delay time will be reduced.

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“…Through the successive stage parallel adder circuit as shown in fig. 5, 0110 is added to the medieval sum output if result is greater than 9 [10][11][12][13].…”

Section: Methodsmentioning

confidence: 99%

Design of BCD Adder using Quantum Cellular Automata

J¹

2020

IJATCSE

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“…It displays the 16 digital outputs i.e., from (s0 to s16) that were produced in relation to the input clock [40,41]. The SAR-register bits are set and reset during each clock cycle, and at the conclusion of the 16th clock, the output of the SAR contains all of the 16-word bits.…”

Section: Sarmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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“…Some of the articles discussed and reviewed the various types of ADC and different calibration methods for timing skews in ADCs [44][45][46][47][48][49][50][51]. The SAR ADC [52][53][54][55][56] with pipelined ADC [57,58] combination is popularly in trend to get good performance from ADC along with CMOS scaling [59]. The reconfigurable ADC [60][61][62][63][64] are in research using pipelined and SAR ADCs to configure the resolution and sampling rate depending upon the requirements.…”

Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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Design of low power 10GS/s 6-Bit DAC using CMOS technology

Cited by 6 publications

References 4 publications

Design of BCD Adder using Quantum Cellular Automata

Design of BCD Adder using Quantum Cellular Automata

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Analog to Digital Converters (ADC): A Literature Review

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Design of low power 10GS/s 6-Bit DAC using CMOS technology

Cited by 6 publications

References 4 publications

Design of BCD Adder using Quantum Cellular Automata

Design of BCD Adder using Quantum Cellular Automata

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Analog to Digital Converters (ADC): A Literature Review

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Product

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Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications