Design of high-speed, wide-band MOS oscillators for monolithic phase-locked loop applications

Banu, M.

doi:10.1109/iscas.1988.15256

Cited by 2 publications

(7 citation statements)

References 5 publications

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“…In this thesis, we only discuss a cascaded MASH 1-1 DSM adopt in our prototype. From the above signal flow, the output of the first quantizer is 5) and the second quantizer output is…”

Section: Fractional-n Divider Pllmentioning

confidence: 99%

“…where is an integer that ( + More generally, if there are phases to be selected, the output frequency would be = ( + ) , (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21) and the tuning step would be ∆ = . (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21)(22) This means that a finer tuning step can be achieved with more phases provided. The average shifted phase number during each is thus…”

Section: Constant-step Phase Switchingmentioning

confidence: 99%

“…Note that although the XRO experiences two mode switches in one measurement cycle, By equaling (4-7) and (4)(5)(6)(7)(8), the input-referred noise can be expressed as…”

Section: Proposed Noise Model For Controlled Oscillator-based Tdcsmentioning

confidence: 99%

“…It was the time when designers faced many challenges when fabricating RF circuits on CMOS process. However, many of these challenges have been resolved, such as high-quality on-chip inductors [1]- [4], wide-band CMOS oscillators [5]- [7], CMOS low-noise amplifiers [8]- [10], etc. Moreover, due to the surge of consumer electronics such 2 as smartphones and entertainment electronics, wireless applications evolve towards low power, small dimensions, higher yield, and higher level of integration owing to its low cost.…”

mentioning

confidence: 99%

“…As will be seen later, this is much lower than the contribution from phase noise of the oscillator. However, (4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15) does limit the signal bandwidth as the quantization noise increases dramatically with .…”

mentioning

confidence: 99%

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In-band phase noise reduction techniques for phase-locked loops in advanced CMOS technologies

Liang¹

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Phase-locked loops (PLLs) have been successfully used as frequency synthesizers for decades in complementary metal-oxide-semiconductor (CMOS) transceivers for wireless communications. However, modern developments in communications require PLLs with wider loop bandwidth and lower in-band phase noise. High in-band phase noise leads to serious consequences in communications, such as degraded signal-to-noise ratio (SNR) and constellation diagram, resulting in low communication quality. Therefore, low PLL in-band phase noise is crucial to the overall transceiver performance, especially in future high-speed high-quality wireless communications. Unfortunately, frequency synthesizers based on conventional PLL structures are facing challenges because their in-band phase noise is often limited by the phase detectors and charge pumps. Noises from these components are amplified due to the structure of the conventional PLLs. Furthermore, PLL often needs to achieve short settling time for some communication standards, and has to provide multi-phase output in some transceiver architectures. Inspired by these requirements, this thesis aims to enhance PLL in-band phase noise performance while meeting other important requirements of future wireless communications in the multi-GHz band.

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“…In this thesis, we only discuss a cascaded MASH 1-1 DSM adopt in our prototype. From the above signal flow, the output of the first quantizer is 5) and the second quantizer output is…”

Section: Fractional-n Divider Pllmentioning

confidence: 99%

Section: Constant-step Phase Switchingmentioning

confidence: 99%

“…Note that although the XRO experiences two mode switches in one measurement cycle, By equaling (4-7) and (4)(5)(6)(7)(8), the input-referred noise can be expressed as…”

Section: Proposed Noise Model For Controlled Oscillator-based Tdcsmentioning

confidence: 99%

mentioning

confidence: 99%