Design of High Speed, Reconfigurable Multiple ICs Tester using FPGA Platform

Rabakavi, Basavaraj; Siddamal, Saroja V.

doi:10.1109/iceeccot43722.2018.9001588

Cited by 5 publications

(5 citation statements)

References 6 publications

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“…This paper is an extension of previous work originally presented in the 3 rd IEEE International Conference on Electrical, Electronics, Communication, Computers and Optimization Techniques [1]. Integrated Circuits which are more commonly known as ICs, are the central components of every electronic circuits present in modern times.…”

Section: Introductionmentioning

confidence: 94%

“…In previous work [1], Dual IC testing of digital ICs was implemented with feature of functionality test only. In this paper, work is extended to perform propagation delay test, operating frequency test with Quad IC testing simultaneously and also to analyze the power consumption and throughput of the proposed testing system.…”

Section: Contributionsmentioning

confidence: 99%

“…If there are no issues like tester downtime and chip contacting problems then test time was considered as valid [20]. The total testing time of a device Ts (Single site test time) can be written as shown in equation (1). 2.…”

Section: Concept Of Multi-site Testingmentioning

confidence: 99%

“…Dual IC testing presented in paper [1], the Decoder (74138-SOIC) and XOR (7486-DIP) ICs were tested simultaneously. The 7486 -XOR IC was tested by applying all possible test vectors to each gate simultaneously and latched outputs were compared with desired values.…”

Section: Dual Ic Testing (Dip and Soic Package)mentioning

confidence: 99%

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Design and Implementation of Quad-Site Testing on FPGA Platform

Rabakavi¹,

Siddamal²

2020

Adv. sci. technol. eng. syst. j.

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As manufacturing efficiency has become a main focus of today's business, it is very critical to surge the throughput by developing different test strategies. With throughput, testing cost also has been recognized as the major challenge in the future of leading semiconductors. Reducing test time is a significant effort to maximize throughput as the complexity increases in future generation outcomes and devices. So, low-cost Automatic Test Equipment (ATE) with parallel test can be promoted as the obvious solution for challenges said above. In parallel testing, multiple devices-under-test (DUT) can be tested at a time that enhances way of testing by increasing product flow, limiting gross test times, and efficient usage of tester. The proposed Integrated Circuit (IC) tester is used to implement multi-site testing (Quad-Site testing) and concurrent testing. It exhibits multi-site efficiency which substantially enhances the throughput by reducing test time. Modular, re-configurable test system provides cost-saving solution. To confirm these effects, authors have presented experimental results for Quad site testing of different ICs namely Decoder, Buffer, Multiplexer and Logic gates. This portable IC Tester handles variety of IC packages like Dual Inline Package (DIP), Small Outline Integrated Circuit (SOIC), Thin Shrink Small Outline Package (TSSOP). With functional test, the proposed tester also verified the AC Parametric tests (i) Propagation Delay is 20ns (ii) Operating frequency with 50MHz for Decoder IC (74HC138). The proposed IC tester consumes 70% less power and throughput enhanced by 11% compared to existing IC testers.

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Section: Introductionmentioning

confidence: 94%

Section: Contributionsmentioning

confidence: 99%

Section: Concept Of Multi-site Testingmentioning

confidence: 99%

Section: Dual Ic Testing (Dip and Soic Package)mentioning

confidence: 99%

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Design and Implementation of Quad-Site Testing on FPGA Platform

Rabakavi¹,

Siddamal²

2020

Adv. sci. technol. eng. syst. j.

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“…For example, Nawarathna [12] designed a test device with 16 digital I/O interfaces that support testing of NAND gate circuits. Rabakavi [13] used an FPGA to conduct functional tests on simple chips like 7408 and 74,138. Vanitha [14] proposed an FPGA-based automatic test device for detecting behavioral faults in digital components such as flipflops, multiplexers, and full adders.…”

Section: Related Workmentioning

confidence: 99%

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Zhang,

Liu,

et al. 2024

Electronics

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The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

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Design of Integrated Circuit Auxiliary Testing Scheme Based on FPGA

Wang,

Ren

et al. 2024

2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE)

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Design of High Speed, Reconfigurable Multiple ICs Tester using FPGA Platform

Cited by 5 publications

References 6 publications

Design and Implementation of Quad-Site Testing on FPGA Platform

Design and Implementation of Quad-Site Testing on FPGA Platform

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Design of Integrated Circuit Auxiliary Testing Scheme Based on FPGA

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