Design of high speed and low power 15-4 compressor

The processor is greatly hampered by the large dataset of picture or multimedia data. The logic of approximation hardware is moving in the direction of multimedia processing with a given amount of acceptable mistake. This study proposes various higher-order approximate counter-based compressor (CBC) using input shuffled 6:3 CBC. In the Wallace multiplier using a CBC is a significant factor in partial product reduction. So the design of 10-4, 11-4, 12-4, 13-4 and 14-4 CBC are proposed in this paper using an input shuffled 6:3 compressor to attain two stage multiplications. The input shuffling aims to reduce the output combination of the 6:3 compressor from 64 to 27. Design of 15-4, 10-4, 9-4, and 7-3 CBCs are performed using the proposed 6:3 compressor and the results obtained are compared with the existing models. These existing models are constructed using multiplexers and 5-3 CBC. When compared to input shuffled 5-3 the proposed 6:3 compressor shows better results in terms of area, power and delay. An approximation is performed on the 6:3 compressor to further reduce the computational energy of the system which is optimal for multimedia applications. The major contribution of this work is the development of two stage multiplier using various proposed CBC. All designs of the approximate compressor (AC) and true compressor (TC) are analysed with 8 x 8 and 16 x 16 image multiplication. The proposed multipliers also provide adequate levels of accuracy, according to the MATLAB simulations, in addition to greater hardware efficiency. As the result approximate circuits over image processing shows the stunning performance in many deep learning network in the current research which is only oriented to multimedia.

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“…Here the 5-3 CBC is constructed using XOR and MUX. The modified 5-3 CBC used in 15-4 CBC was proposed in [19] as shown in Fig. 3.…”

Section: Literture 21 Compressormentioning

confidence: 99%

Optimized Image Multiplication with Approximate Counter Based Compressor

Savio¹,

Deepa²,

Bharathiraja³

et al. 2022

Computers, Materials &Amp; Continua

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“…This Section proposed a novel 15:4 counter [5] design using the proposed 5:3 counter of the above Section and optimised the parallel adder of the final stage. The proposed 15:4 counter consists of five numbers of full adders connected in parallel in stage one.…”

Section: Proposed High‐speed Multiplier Design Using Proposed Countersmentioning

confidence: 99%

“…The authors have used their proposed 5:3 counter to design 15:4 counter [4]. Authors [5] have proposed a 15:4 counter using a 5:3 counter. The 5:3 counter design of Marimuthu et al [5] has shown in the Figure 5.…”

Section: Literature Reviewmentioning

confidence: 99%

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Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

Krishna¹,

Neeharika

Janjirala³

et al. 2020

IET Computers & Digital Tech

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This paper proposes an efficient approach to design high-speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re-ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…The basic architecture of 15-4 compressor [2] is shown in Figure 9.This will compress 15 partial products into four outputs. It has five full adders and two 5-3 compressors and one parallel adder.…”

Section: Design Of 15-4 Compressormentioning

confidence: 99%

Design and Implementation of 15-4 Compressor Using 1-Bit Semi Domino Full Adder at 28nm Technology

.¹

2015

IJRET

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In this paper, we present 15-4 Compressor for Digital signal processing. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5:3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this Work is to inspect the power, delay, power delay product of full adders in different logic styles and to inspect power, delay, and power delay product of Semi domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V, 500MHz frequency evaluated by the comparing of the simulation results obtained from Cadence spectre.

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Design of high speed and low power 15-4 compressor

Cited by 21 publications

References 7 publications

Optimized Image Multiplication with Approximate Counter Based Compressor

Optimized Image Multiplication with Approximate Counter Based Compressor

Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

Design and Implementation of 15-4 Compressor Using 1-Bit Semi Domino Full Adder at 28nm Technology

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