Design of high performance 16 bit multiplier using vedic multiplication algorithm with McCMOS technique

Gupta, Radheshyam; Dhar, Rajdeep; Baishnab, Krishna Lal; Mehedi, Jishan

doi:10.1109/icgccee.2014.6922296

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…The result shows the significant improvement. The Vedic multiplier using McCMOS (Multi Channel CMOS) with 65 nm and 45 nm technology is proposed in [3] [4]. The power delay product is reduced from 48% to 70% using this technology.…”

Section: Introductionmentioning

confidence: 99%

Implementation of N-Bit Binary Multiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Angeline¹,

Valarmathy²

2016

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This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N − 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N − 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.

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Section: Introductionmentioning

confidence: 99%

Implementation of N-Bit Binary Multiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Angeline¹,

Valarmathy²

2016

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“…Radheshyam Gupta et al described 16 bit Vedic multiplier using McCMOS technique at 45nm technology [9]. The Vedic Multiplier UrdhvaTiryakbhyam is approximately 10 times faster than the conventional multiplier.…”

Section: Related Workmentioning

confidence: 99%

Design of Low Power High Speed Adders in McCMOS Technique

Sharma¹

2015

IJIRSET

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ABSTRACT:Adder are the core component of processors and digital design architecture. Also, not only addition, but performs many other arithmetic operations such as subtraction, division and multiplication. The focus of VLSI technology is to reduce power consumption, enhancing the performance and speed of a digital circuit. Less power consumption is the ultimate attention for any computation. In this paper, 16 bit adders are designed using one such technique i.e. McCMOS and compared for power dissipation, delay, leakage power and power delay product. Different types of adders have been designed using Multiple channel CMOS (McCMOS) technology and compared with conventional with 45nm technology. The simulation result shows that the average power reduces to 30 -35% less and PDP is reduced to 15-17% than the power and PDP of the conventional CMOS. Hence the technique can be used for low leakage high speed application. The simulation has been carried out in tanner tool EDA 14.1 with 1V power supply.

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Implementation for minimization of computation time of partial products for designing multipliers

Fatima¹,

Shrman²,

Jain³

2016

2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)

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Design of high performance 16 bit multiplier using vedic multiplication algorithm with McCMOS technique

Cited by 5 publications

References 6 publications

Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Design of Low Power High Speed Adders in McCMOS Technique

Implementation for minimization of computation time of partial products for designing multipliers

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Design of high performance 16 bit multiplier using vedic multiplication algorithm with McCMOS technique

Cited by 5 publications

References 6 publications

Implementation of &lt;i&gt;N&lt;/i&gt;-Bit Binary Multiplication Using &lt;i&gt;N&lt;/i&gt; - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Implementation of &lt;i&gt;N&lt;/i&gt;-Bit Binary Multiplication Using &lt;i&gt;N&lt;/i&gt; - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Design of Low Power High Speed Adders in McCMOS Technique

Implementation for minimization of computation time of partial products for designing multipliers

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Product

Resources

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Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method