Design of high gain CMOS LNA with improved linearity using modified derivative superposition

Abstract

This paper presents a highly-linear high-gain low noise amplifier (LNA) based on the inter stage technique. The linearized LNA is achieved by using the linear cascode amplifier as output stage utilizing a modified derivative superposition method and functionality is analyzed using Volterra series. Using simulations in 0.18μm CMOS technology, the IIP 3 is improved by more than 37dBm reaching to +3dBm, with the cost of decrease 10dB gain at 5.7GHz frequency band. The LNA consumes 18.7mW power under 1.8V supply voltage. Compared to previously published LNA designs, the proposed LNA has the smallest noise figure of 2.1 dB, highest gain 21.5 dB, and the highest Figure of Merit of 3.15.