Design of FPGA interconnect for multilevel metallization

Abstract

Abstract-How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's mesh-of-trees (MoT), which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size ( ), our network requires only ( ) area; this is in stark contrast to traditional, Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in . In practice, we show that, even for the admittedly small designs in the Toronto "FPGA Place and Route Challenge," arity-4 MoT networks require 26% fewer switches than the standard, Manhattan FPGA routing scheme.Index Terms-Field programmable gate array (FPGA), hierarchical, interconnect, mesh-of-trees (MoT), multilevel metallization, Rent's rule.

Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies

“…Previous works [10][11][12], also confirms the multilevel BFT based 2D interconnect topology is able to reduce 59 % of the total number of switches and save 56 % of the total FPGA area compared to Mesh-based FPGA with identical logic density and array size [10]. Considering the challenges associated with 2D physical design of Tree-based FPGA [13,14], we proposed two different network partitioning methodology to design and implement high density 3D FPGAs based on Tree-based interconnect network. The main focus of this chapter is on the discussion of the complete set of tools and technologies needed to conduct 3D design feasibility study and interconnect network characterization methodologies to build high performance 3D re-configurable systems based on Tree-based interconnect and a comparison procedure has been put in place and the end to validate the advantages of 3D Tree-based FPGA over 3D Mesh-based FPGA architectures.…”

“…The interconnect delay of Treebased architecture increases exponentially [10,14,18] as the Tree grows to higher levels. Horizontal partitioning methodology is introduced optimize the exponential rise in Tree network delay as the Tree grows to higher levels.…”

Evaluating on-chip interconnects for low operating frequency silicon neuron arrays

“…The crosspoint architecture uses dedicated wires to statically route events between neurons. This routing methodology is used commonly in FPGA designs [14], which share the fundamental problem of efficiently connecting large numbers of computational blocks with a configurable interconnect. While full NxN neural interconnectivity would be prohibitively large in terms of area, it is unnecessary, as the biological systems that we are emulating have limited fanout and connectivity.…”

An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing

“…Figure 2 shows the MoT topology of [5] with four PCs and four memory modules (MMs). Unlike earlier MoT topologies of [8,12,13], PCs and MMs are placed at the roots of the trees instead of the leaves. The MoT network consists of two main structures: a set of fan-out trees and a set of fan-in trees Figure 2(b) shows the binary fan-out trees, where each PC is a root and connects to two children, and each child has two children of their own.…”