Design of FinFET and GnrFET Based Full Adder Cell Using Multiplexer Selection Logic

Florance, D. Rebecca; Prabhakar, B.

doi:10.1109/icssit53264.2022.9716389

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Table 6 compares the performance of the proposed CISFA with various state of art models like RHMFA [10], HFFA [11], IMC-FA [12], CTFA [13], and MFA [18]. From the simulations, it is observed that the proposed CISFA resulted in superior performance, because the CISFA utilizes the advanced path selection mechanisms.…”

Section: Resultsmentioning

confidence: 99%

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Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Florance

Prabhakar

Mishra

2022

Journal of Nanomaterials

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Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay-controlled hybrid adder (DCHA) and delay-controlled hybrid subtractor (DCHS) are developed using these full adders. In addition, a unified delay-controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR-ALU is developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed nanotechnology-based models outperformed the conventional adders and subtractors in terms of area, power, and delay reduction.

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Section: Resultsmentioning

confidence: 99%

“…Based on the modifications of CSLA, the performances were compared with other adders. By the BEC modification instead of MFA [18] chain, the logic converter provides the circuit with slight changes of delay.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Florance

Prabhakar

Mishra

2022

Journal of Nanomaterials

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Design and analysis of a low power high speed full adder using 2×1 multiplexer

Singh¹,

Kumar²

2022

2022 IEEE North Karnataka Subsection Flagship International Conference (NKCon)

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Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Sharma

Haq

2023

CNANO

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Background: The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology. Objective: FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared. Methods: An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP). Results: The full adders using FinFETs show less leakage power and PDP. The AND-OR logic-based hybrid full adder using FinFETs shows the least energy consumption per switching. FinFET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation. Conclusion: MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultra-nanoscale regime.

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Design of FinFET and GnrFET Based Full Adder Cell Using Multiplexer Selection Logic

Cited by 3 publications

References 8 publications

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Design and analysis of a low power high speed full adder using 2×1 multiplexer

Review of the Nanoscale FinFET Device for the Applications in Nano-regime

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