Design of Efficient Scan Flip-Flop

Nagesh, B. K.; Chandra, Budiman

doi:10.1109/rteict52294.2021.9573924

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…In r_data, the transmitter rs232_tx transmits serial data based on bit count [12]. A done signal is issued when the transmission is stopped by setting the state to low level when the bit count reaches 10 and the bit flag is at a high level [21][22][23].…”

Section: Experiments Codes 61 Uart Transmitter Modulementioning

confidence: 99%

Design and Implementation of Verilog Based High Speed Low Power UART

Ms. Banti Kumari,

Ms. Kanika Jindal,

Mr. Amit Bindal

2024

Int Res J Adv Engg Hub

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The most crucial component of serial communication is a microcircuit called a universal asynchronous receiver/transmitter (UART). Receive-transmitter asynchronous technology is known as UART, and it is widely used for device-to-device communication protocols. Using asynchronous serial communication at a speed that can be adjusted. A hardware communication technique called UART Asynchronous conditions occur when the output of the transmitting device and the receiving end are not in sync with a clock. In UART, receiving a signal is known as RxD, and transmitting a signal is known as TxD. In comparison to the existing conventional UART design, we were able to reduce delay by 29% and power usage by 33% using our approach. The effectiveness of the novel UART design is noticed with the reduction in delay and power consumption. Synthesis and simulation are done in Xilinx ISE and Modelsim and Verilog HDL is used to implement a unique UART design.

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Section: Experiments Codes 61 Uart Transmitter Modulementioning

confidence: 99%

Design and Implementation of Verilog Based High Speed Low Power UART

Ms. Banti Kumari,

Ms. Kanika Jindal,

Mr. Amit Bindal

2024

Int Res J Adv Engg Hub

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“…By using simple exclusive or (XOR) gates, a stateskipping LFSR is developed, which reduces the amount of test patterns and delays through hardware. Two innovative and effective Scan flipflop designs that use less power, space, and delay have been used in [5]. Cadence Virtuoso was used to develop the two initial Scan flip-flop designs, a modified Transmission Gate based Scan flip-flop and a Gate Diffusion Input based D flip-flop.…”

Section: Literature Surveymentioning

confidence: 99%

Low Power Full Scan Architecture for UART Module

Abhinav¹,

Kiran²

2022

Int J Res Rev

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Modern SoCs feature a complicated design made up of many macros that are in charge of various tasks carried out by an application. The effort required for the verification and testing of a specific product grows as a result of the requirement for more raw computing power and an increase in integration density. The testability of the communication modules is required because SoCs contain several communication modules that, if they fail, could render the SoC worthless. The full scan architecture for a full-duplex UART module is the one that is being suggested. The work displays the power savings for both manually and automatically inserted scan chains that were based on the system partition algorithms. While manually placed scan chains achieved peak power reduction of 74.9 percent in comparison to automatic scan chains, the automatically inserted scan chains have less area with higher activity. Keywords: Low power, full scan, UART, DFT, System partition algorithms

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“…Speed was noticed to be faster in functional and test modes. [11]. When the slave device cannot accept any more data, a unique technique called clock stretching is used.…”

Section: Literature Reviewmentioning

confidence: 99%

I2C Master Scan Chain Insertion and Functional Coverage

2022

Int J Res Rev

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I2C is a serial, bidirectional bus for communication that Philips Semiconductors created. only two bus lines are needed a (SDA) serial data line and a (SCL) serial clock line. With the addition of scan chains, a method for I2C Bus testing has been implemented in this study. In order to achieve the necessary requirements, the number of scan chain insertions is predetermined. The coverage of the Functions is also performed to verify the test bench. Keywords: I2C, Scan Chain, Coverage, Testing, Design for test

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Design of Efficient Scan Flip-Flop

Cited by 6 publications

References 11 publications

Design and Implementation of Verilog Based High Speed Low Power UART

Design and Implementation of Verilog Based High Speed Low Power UART

Low Power Full Scan Architecture for UART Module

I2C Master Scan Chain Insertion and Functional Coverage

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