I2C is a serial, bidirectional bus for communication that Philips Semiconductors created. only two bus lines are needed a (SDA) serial data line and a (SCL) serial clock line. With the addition of scan chains, a method for I2C Bus testing has been implemented in this study. In order to achieve the necessary requirements, the number of scan chain insertions is predetermined. The coverage of the Functions is also performed to verify the test bench.
Keywords: I2C, Scan Chain, Coverage, Testing, Design for test
The variousi analyses are based primarily on arithmetici circuit, notably with MUX designi, however this paper also investigates using a multiplexer to reduce power consumption. A 4:1 MUX is designed using CMOS transmission gatei logic (TGL), which hasi lower circuit complexity than traditional CMOS-based multiplexers. The NMOS and PMOS are coupled fori a strongi output leveli with a gaini in area, which is the centrali outcome of the proposed MUX. The designed circuit is dissipating 27.93 μW from a 1.8 V supply voltage in comparison to 43.85 μW of conventionali full adder.
Keywords: Mux, Full Adder, Transmission Gate, CMOS.
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