Design of Dual-Gate P-type IMOS Based Industrial Purpose Pressure Sensor

Solay, Leo Raj; Singh, Sarabdeep; Kumar, Naveen; Amin, S. Intekhab; Anand, Sunny

doi:10.1007/s12633-020-00785-8

Cited by 10 publications

(6 citation statements)

References 23 publications

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“…In 2020 [14,15], Nanowire GAAFET-based NEMS pressure sensor is designed to increase the electrostatic controllability, which further improves the sensitivity of the pressure sensor device. The IMOS-based pressure sensor was developed in 2021 [16] that provides improved sensitivity, as IMOS has a lower subthreshold swing and higher switching speed as compared to MOSFET. In 2023 [17], nano-cantilever pressure sensor based on TFET technology has been designed which performs better than MOSFET technology-based pressure sensor.…”

Section: Introductionmentioning

confidence: 99%

Pressure sensor based on Hetero-stack L-shape TFET: simulation study

Shukla,

Khosla,

Sood

et al. 2024

Phys. Scr.

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In this paper, the first-time-ever pressure sensor based on Hetero-stack L-shape TFET has been proposed and investigated through the SILVACO ATLAS TCAD tool. Owing to the hetero-stacking of Germanium material and Silicon material, an enhanced Ion and reduced sub-threshold swing is obtained by the proposed device leading to enhanced Pressure sensor sensitivity. The basic working principle of this proposed pressure sensor device is when pressure is applied to the diaphragm, the diaphragm bends which varies the metal-dielectric thickness of the oxide layer which further alters the electrical characteristics of the proposed pressure sensor. The diaphragm bendings considered in the study are 0, 1, 2, and 2.5 nm. The performance of the proposed pressure sensor device is analyzed through different electrical performance characteristics such as energy band diagrams, electric field, potential, Ion, sub-threshold swing, electron band-to-band tunneling rate, and various other analog/RF parameters at different diaphragm bendings. The effects of ITCs at various bendings are also analyzed to provide an in-depth effect of the factors that might affect the performance of the sensor. The proposed sensor design will be proven as a milestone in the array of sensors built for ultra-sensitive pressure sensing applications.

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Section: Introductionmentioning

confidence: 99%

Pressure sensor based on Hetero-stack L-shape TFET: simulation study

Shukla,

Khosla,

Sood

et al. 2024

Phys. Scr.

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“…Several proposed devices, including tunnel field effect transistors (TFETs) [4], nano-electromechanical field effect transistors [5], and impact ionization MOS [6], have promising features such as low subthreshold swing (SS) and high I ON /I OFF ratio. TFETs are the next best alternative device [7] for transistor downscaling with reduced SCEs. TFETs have a PIN structure that results in band-to-band tunneling, which has a substantial effect on low-power applications [8].…”

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Solay

Kumar²,

Amin³

et al. 2022

Semicond. Sci. Technol.

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In this paper, a novel low power consumption device based on dopingless gate all around nanowire tunnel field effect transistor with negative capacitance effect is proposed. Negative capacitance is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, VT and SS are dropped significantly to less than 60mV/decade. Negative capacitance makes significant contribution to the device performance by lowering operating voltage for low power applications. To calculate the optimum bias, Landau-Khalatnikov (L-K) equation has been used. To evaluate the influence of negative capacitance, ferroelectric (FE) material PZT (lead zirconate titanate) – ceramic material which has perovskite properties has been used as gate insulator. Thus, gate all around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA negative capacitance DL NW TFET (GAA NC DL NW TFET). PZT has an appropriate polarization rate, high dielectric capacitance and high degree of reliability. To achieve SS lower than 60mV/decade at lower VT, effective tuning of FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device structure. Aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of doping-less technique to the nanowire based TFET. The enhancement of the on-state current at reduced supply voltage of silicon based TFET devices with improved steep subthreshold swing which has been addressed with the help of NC technique. With the application of NC technique, the proposed device showcased an improved 4 (µA/µm) of ION, 1012 of current ratio. Additionally, influence of variation in FE thickness (tFE) on performance parameters are examined. The proposed device structure, GAA NC DL NW TFET operates at minimum operating voltage than GAA DL NW TFET making it as an ideal choice for low power voltage applications

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“…To surpass the SCEs, devices like Tunnel-FET (TFETs) [13][14], Impact Ionization MOS (IMOS) [15] and novel structured designs such as three-dimensional (3D) structures [16], multi-gate designs such as tri-gate structures [17][18] for improved controllability over gate and gate-all-around (GAA) structure designs with high packaging density and excellent gate controllability over the channel were considered as the best replacements [19]. With the applications include clinical purpose biosensors [20], industrial based pressure sensors [21] etc. Among the mentioned alternatives with advantages like transport properties, electrostatic control, and reduced SCEs, the GAA structures turn out to be a promising design alternative [22].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Common Source Amplifier Circuit Application Using Gate Stack Based Gate-all-around Charge Plasma Nanowire FET

Solay¹,

Kumar²,

Amin

et al. 2022

Preprint

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The reported work demonstrates the application of common source amplifier circuit using gate-all-around gate stacked charge plasma nanowire field effect transistor (GAA GS CP NW FET). Primarily, the impact of the gate stacking (GS) technique upon the Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA CP NW FET) structure is explored. In which GAA GS CP NW FET structure resulted in excellent electrostatic control over the channel by incorporating the advantages of GAA structures. The transfer characteristics have been enhanced with the gate stacking (SiO2 + high k) technique when employed at the dielectric region of the structure. The charge plasma concept which is applied in the proposed device helped in reducing the threshold voltage fluctuations. A contrast is drawn between GAA CP NW FET and GAA GS CP NW FET structures in terms of analog and RF analysis. Linearity parametric analysis were made to examine the distortion less digital communication and a comparison is made between the structures. The proposed structure is then utilized for designing a common source amplifier circuit and contrasted with the GAA CP NW FET structure. With the applied gate stacking technique, the proposed structure resulted in improved ON-current, reduced OFF-current, enhanced current ratio. The CS amplifier circuit application resulted in improved Vout and gain attributes with the proposed GAA GS CP NW FET structure when compared with Metal Oxide Semiconductor FET (MOSFET), Tunnel FET (TFET) and GAA CP NW FET structure proving its capability for forthcoming nanoscale circuit applications.

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Design of Dual-Gate P-type IMOS Based Industrial Purpose Pressure Sensor

Cited by 10 publications

References 23 publications

Pressure sensor based on Hetero-stack L-shape TFET: simulation study

Pressure sensor based on Hetero-stack L-shape TFET: simulation study

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Investigation of Common Source Amplifier Circuit Application Using Gate Stack Based Gate-all-around Charge Plasma Nanowire FET

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