Design of double-sampling /spl Sigma//spl Delta/ modulation A/D converters with bilinear integrators

Rombouts, Pieter; Maeyer, Jeroen De; Weyten, L.

doi:10.1109/tcsi.2005.844233

Cited by 16 publications

(13 citation statements)

References 13 publications

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“…However, because of the bilinear factor (1 + z −1 ) in the numerator of eq. (2), the modulator architecture should be modified [7]. The modified architecture for a 2 nd order modulator is shown in Fig.…”

Section: Double-samplingmentioning

confidence: 99%

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A 8 mW 72 dB ΣΔ-modulator ADC with 2.4 MHz BW in 130 nm CMOS

Bock

Rombouts

2011

Analog Integr Circ Sig Process

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A double-sampling split Σ∆-ADC with bilinear integrators and a 7-level quantizer is presented. It achieves third order noise shaping with a second order modulator through quantization noise-coupling. The modulator is integrated in a 130 nm CMOS technology. For a clock frequency of 48 MHz and an oversampling ratio of 20 (2.4 MHz signal bandwidth), it achieves 72 dB DR and 68 dB SNR. The prototype consumes 8 mW from a 1.2 V voltage supply.

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Section: Double-samplingmentioning

confidence: 99%

“…The modulator also shows an additional parameter b 3 . This gives the necessary freedom to design the NTF at will [7]. …”

Section: Double-samplingmentioning

confidence: 99%

A 8 mW 72 dB ΣΔ-modulator ADC with 2.4 MHz BW in 130 nm CMOS

Bock

Rombouts

2011

Analog Integr Circ Sig Process

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“…The fully floating bilinear structure can reject the interferer. A trivial adjustment is necessary to increase the freedom to completely control the pole position of NTF [6] . The double-sampling cascade 2-1-1 multi-mode modulator topology with single-bit quantizers is proposed and shown in Figure 2.…”

Section: Proposed Modulator Topologymentioning

confidence: 99%

“…The feed-forward path can decrease the output swings greatly [6] . Figure 3 compares the output swing of the 1 st and 2 nd integrators in the modulators with and without the feed-forward path.…”

Section: Gsm and Bluetooth Modementioning

confidence: 99%

A Reconfigurable Double Sampling Sigma Delta Modulator for 4G Wireless Receivers

Tang

2010

2010 International Conference on Communications and Mobile Computing

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A reconfigurable cascade sigma delta modulator with single-bit quantizers for multi-mode zero-IF receivers has been presented on the system level. The modulator was based on single-bit quantizers and utilized feed-forward path to increase the dynamic range. The double-sampling technique was adopted to improve the over-sampling ratio (OSR) over a wide bandwidth range. The loop order and OSR were reconfigurable to meet the requirements of a wide range of standards. The coefficient scaling was deduced to obtain the desired noise shaping. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in MATLAB/ SIMULINK to extract the required circuit parameters. A peak SNDR of 85/ 85/ 67/ 65/ 57/ 48 dB is achieved over a 0.2/ 1/ 2/ 3.84/ 22/ 28 MHz channel bandwidth at a sampling frequency of 25.6/ 128/ 48/ 84.5/ 264/ 280 MHz for GSM/ Bluetooth/ GPS / WCDMA/ WLAN/ WiMAX mode. The proposed modulator fulfills the performance requirements of 4G mobile communication standards.

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“…We refer to this as the architectural problem. Note that this also appears to be an issue in some advanced electrical A/D converters [13], [14]. Clearly, the architectural problem would be solved if we were able to find a force-feedback architecture that provides enough degrees-of-freedom, allowing the placement of the NTF poles at arbitrary positions.…”

Section: Introductionmentioning

confidence: 99%

An Unconstrained Architecture for Systematic Design of Higher Order $\Sigma\Delta$ Force-Feedback Loops

Raman

Rombouts

Weyten

2008

IEEE Trans. Circuits Syst. I

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Nowadays, 61-modulation is a widely used technique for analog-to-digital (A/D) conversion, especially when aiming for high resolutions. While being applied initially for purely electrical A/D converters, its application has been expanded to mixed mechanical-electrical systems. This has led to the use of 61 force-feedback for digital readout of high-performance inertial sensors. However, compared with their electrical counterpoint, 61 force-feedback loops often have to deal with three additional issues: 1) an increased stability problem due to phase-lag occurring in the sensor; 2) the injection of relatively high levels of readout noise in the loop; and 3) the lack of degrees-of-freedom of many 61 force-feedback architectures for implementing an arbitrary noise transfer function. As a result, 61 force-feedback loops found in literature are designed in a much less systematic way as compared with electrical 61 modulators. In this paper, we address these issues and propose a new unconstrained architecture. Based on this architecture, we are able to present a systematic approach for designing 61 force-feedback loops. Additionally, the main strengths and weaknesses of different 61 force-feedback architectures are discussed. Index Terms-A/D-conversion, force-feedback, MEMS inertialsensors, sigma-delta (61) modulation, systematic design.

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Design of double-sampling /spl Sigma//spl Delta/ modulation A/D converters with bilinear integrators

Cited by 16 publications

References 13 publications

A 8 mW 72 dB ΣΔ-modulator ADC with 2.4 MHz BW in 130 nm CMOS

A 8 mW 72 dB ΣΔ-modulator ADC with 2.4 MHz BW in 130 nm CMOS

A Reconfigurable Double Sampling Sigma Delta Modulator for 4G Wireless Receivers

An Unconstrained Architecture for Systematic Design of Higher Order $\Sigma\Delta$ Force-Feedback Loops

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