2012 13th International Conference on Electronic Packaging Technology &Amp; High Density Packaging 2012
DOI: 10.1109/icept-hdp.2012.6474684
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Design of die-pad on exposed substrate (DOES) leadframe package for DDR3 interface applications

Abstract: The fabless semiconductor companies always use the mature packages provided by the assembly houses. The cost and package selection trade-off shall be taken for different marketing segments. An innovative leadframe package was proposed with a cost competitiveness that increased � ore leads for digital TV applications compared to conventIOnal leadframe package. The full channel from controller chip side to DRAM chip side was simulated and analyzed in the frequency and time domains. Results indicated that sel � c… Show more

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“…With less energy loss in the frequency domain, better high-speed waveforms in the time-domain would be expected. The full channel co-simulations from the DDR3 co � troller chip (I/O) pad to the DRAM chip (I/O) pad usmg the controller I/O netlists designed with the tsmc 40 nm silicon node, the channel S-parameters, and Micron DDR3 v68a netIists [5] were taken in Synopsys HSPICE for 220 ns. Both writing and reading data were at 2 Gb/s with pseudo random bit patterns (PRBP).…”
Section: System Performancementioning
confidence: 99%
“…With less energy loss in the frequency domain, better high-speed waveforms in the time-domain would be expected. The full channel co-simulations from the DDR3 co � troller chip (I/O) pad to the DRAM chip (I/O) pad usmg the controller I/O netlists designed with the tsmc 40 nm silicon node, the channel S-parameters, and Micron DDR3 v68a netIists [5] were taken in Synopsys HSPICE for 220 ns. Both writing and reading data were at 2 Gb/s with pseudo random bit patterns (PRBP).…”
Section: System Performancementioning
confidence: 99%