Design of Belief Propagation Based on FPGA for the Multistereo CAFADIS Camera

Magdaleno, Eduardo; Luke, J. P.; Rodríguez, María Candelaria Gil; Rodríguez-Ramos, José Manuel

doi:10.3390/s101009194

Cited by 9 publications

(10 citation statements)

References 14 publications

(13 reference statements)

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“…Among the these algorithms, the one-dimensional DP algorithm displayed high processing speed, but its error rate was not good, as it is suffered from a problem called streaking, which is caused by comparing only those pixels on the same lines [Kalomiros and Lygouras 2009]. In several hardware systems, two-dimensional global matching algorithms such as BP [Choi and Rutenbar 2012;Magdaleno and Lüke 2010;Pérez et al 2009] and tree-structured DP [Jin and Maruyama 2012a], were implemented. In these systems, the error rates can be improved by repeating the two-dimensional scans, but the processing speed is limited because of the repetition.…”

Section: Related Workmentioning

confidence: 99%

“…Several FPGA systems based on BP have been developed to improve the error rates. The processing speed of BP-2 [Pérez et al 2009] and BP-3 [Magdaleno and Lüke 2010] is very slow (when normalized per pixel). The processing speed of BP-1 is much faster, but in this implementation, all matching costs are stored in on-chip block RAMs.…”

Section: Comparison With Other Stereo Vision Systemsmentioning

confidence: 99%

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Fast and Accurate Stereo Vision System on FPGA

Jin

Matsumoto

2014

ACM Trans. Reconfigurable Technol. Syst.

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In this article, we present a fast and high quality stereo matching algorithm on FPGA using cost aggregation (CA) and fast locally consistent (FLC) dense stereo. In many software programs, global matching algorithms are used in order to obtain accurate disparity maps. Although their error rates are considerably low, their processing speeds are far from that required for real-time processing because of their complex processing sequences. In order to realize real-time processing, many hardware systems have been proposed to date. They have achieved considerably high processing speeds; however, their error rates are not as good as those of software programs, because simple local matching algorithms have been widely used in those systems. In our system, sophisticated local matching algorithms (CA and FLC) that are suitable for FPGA implementation are used to achieve low error rate while maintaining the high processing speed. We evaluate the performance of our circuit on Xilinx Vertex-6 FPGAs. Its error rate is comparable to that of top-level software algorithms, and its processing speed is nearly 2 clock cycles per pixel, which reaches 507.9 fps for 640 × 480 pixel images. ACM Reference Format:Jin, M. and Maruyama, T. 2014. Fast and accurate stereo vision system on FPGA.

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Section: Related Workmentioning

confidence: 99%

Section: Comparison With Other Stereo Vision Systemsmentioning

confidence: 99%

Fast and Accurate Stereo Vision System on FPGA

Jin

Matsumoto

2014

ACM Trans. Reconfigurable Technol. Syst.

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“…Table 11 compares some features of our proposed designs to other approaches. The approach presented in [70] shows an implementation on FPGA of the belief propagation algorithm used in stereo systems. The main drawback with that approach is that a Nx×Ny×K cost volume must be generated to extract the optimal value between K candidate values at each of the Nx×Ny pixels of the output disparity map.…”

Section: Discussionmentioning

confidence: 99%

“…Some light-field rendering algorithms have been implemented [65,66,67], and also some effort has been made to implement wavefront phase estimation in real time [68,69]. One of the first examples of depth from light field on FPGA can be found in [70], where the authors proposed an architecture that implements the belief propagation algorithm and used it on light-field data. On the other hand, Chang et al.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a Depth from Light Field Algorithm on FPGA

Conde

Luke

Rosa

2019

Sensors

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A light field is a four-dimensional function that grabs the intensity of light rays traversing an empty space at each point. The light field can be captured using devices designed specifically for this purpose and it allows one to extract depth information about the scene. Most light-field algorithms require a huge amount of processing power. Fortunately, in recent years, parallel hardware has evolved and enables such volumes of data to be processed. Field programmable gate arrays are one such option. In this paper, we propose two hardware designs that share a common construction block to compute a disparity map from light-field data. The first design employs serial data input into the hardware, while the second employs view parallel input. These designs focus on performing calculations during data read-in and producing results only a few clock cycles after read-in. Several experiments were conducted. First, the influence of using fixed-point arithmetic on accuracy was tested using synthetic light-field data. Also tests on actual light field data were performed. The performance was compared to that of a CPU, as well as an embedded processor. Our designs showed similar performance to the former and outperformed the latter. For further comparison, we also discuss the performance difference between our designs and other designs described in the literature.

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“…The algorithm can be accelerated using parallel processing power of FPGAs instead of other classical technology platforms [15,16]. In our implementation the improvements are due to the fact that:

Arithmetic computations are performed in pipeline and as parallel as possible.

The algorithm is implemented fully in parallel for each color component.

We have used a hardware divider that performs the division operation for the normalization task in a single clock cycle.

…”

Section: Algorithm To Hardwarementioning

confidence: 99%

Super-Resolution in Plenoptic Cameras Using FPGAs

Pérez

Magdaleno

Pérez

et al. 2014

Sensors

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Plenoptic cameras are a new type of sensor that extend the possibilities of current commercial cameras allowing 3D refocusing or the capture of 3D depths. One of the limitations of plenoptic cameras is their limited spatial resolution. In this paper we describe a fast, specialized hardware implementation of a super-resolution algorithm for plenoptic cameras. The algorithm has been designed for field programmable graphic array (FPGA) devices using VHDL (very high speed integrated circuit (VHSIC) hardware description language). With this technology, we obtain an acceleration of several orders of magnitude using its extremely high-performance signal processing capability through parallelism and pipeline architecture. The system has been developed using generics of the VHDL language. This allows a very versatile and parameterizable system. The system user can easily modify parameters such as data width, number of microlenses of the plenoptic camera, their size and shape, and the super-resolution factor. The speed of the algorithm in FPGA has been successfully compared with the execution using a conventional computer for several image sizes and different 3D refocusing planes.

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Design of Belief Propagation Based on FPGA for the Multistereo CAFADIS Camera

Cited by 9 publications

References 14 publications

Fast and Accurate Stereo Vision System on FPGA

Fast and Accurate Stereo Vision System on FPGA

Implementation of a Depth from Light Field Algorithm on FPGA

Super-Resolution in Plenoptic Cameras Using FPGAs

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