Fast and Accurate Stereo Vision System on FPGA

Abstract

In this article, we present a fast and high quality stereo matching algorithm on FPGA using cost aggregation (CA) and fast locally consistent (FLC) dense stereo. In many software programs, global matching algorithms are used in order to obtain accurate disparity maps. Although their error rates are considerably low, their processing speeds are far from that required for real-time processing because of their complex processing sequences. In order to realize real-time processing, many hardware systems have been proposed to date. They have achieved considerably high processing speeds; however, their error rates are not as good as those of software programs, because simple local matching algorithms have been widely used in those systems. In our system, sophisticated local matching algorithms (CA and FLC) that are suitable for FPGA implementation are used to achieve low error rate while maintaining the high processing speed. We evaluate the performance of our circuit on Xilinx Vertex-6 FPGAs. Its error rate is comparable to that of top-level software algorithms, and its processing speed is nearly 2 clock cycles per pixel, which reaches 507.9 fps for 640 × 480 pixel images. ACM Reference Format:Jin, M. and Maruyama, T. 2014. Fast and accurate stereo vision system on FPGA.

High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

“…Table VI gives a comparison of the proposed methodology with state-of-the-art designs in terms of CPF. This table shows that a 44.4% improvement is achieved by the proposed methodology as compared to the design of [23] for all the image resolutions. For the image size 1280x720, the proposed methodology yields about 39.5% better performance in terms of CPF when compared with [22] because of the reduction in the number of samples.…”

“…Fig. 10b gives the comparison of the latest designs [9], [22], [23], [35] with the proposed methodology in terms of the number of cycles needed for computing the disparity of a single frame (CP F = F requency/F P S). The performance of proposed methodology does not degrade with the increase in image size.…”

“…10c. Comparison to [9], [22], [23], [35] in terms of CPF and (c) Comparison in terms of FPGA resource utilization LUTs, Registers (N.M=Not mentioned). …”

“…• Show that the proposed methodology results in improvement of about 44.4% Cycles per Frame (CPF), 52% Frames per Second (FPS) and 61.5% and 59.6% LUT and register utilization respectively compared with the state-of-the art designs [9], [13], [23]. The rest of the paper is organized as follows: Section II provides the necessary theoretical background, Section III introduces the proposed methodology and subsequent architecture, Section IV discusses the experimental results, compares performance of the proposed methodology with existing designs and finally Section V concludes the discussion.…”

A Fuzzy Logic Approach for Stereo Matching Suited for Real-Time Processing

“…In [18], a two step method was proposed where an initial disparity was computed and only reliable disparity values were aggregated to the cost function for the second step. Jin et al [19] proposed a cost aggregation method that computed ground control points (GCP) in order to refine disparity values using the GCPs, while [20] adapted the support area using assumptions of similarity and proximity values. Using the graphics hardware, real-time processing can be achieved, but the implementation must be efficiently adapted and modifications to that structure will be difficult to carry out.…”