Design of Approximate Compressors for Multiplication

Gorantla, Anusha; Deepa, P.

doi:10.1145/3007649

Cited by 53 publications

(28 citation statements)

References 16 publications

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“…Most of the recent multiplier are constructed with compressor. In [12] discrete cosine transform (DCT) operation are done with approximate compressor. In this work many new designs of the approximate multiplier are developed.…”

Section: Multiplier Designmentioning

confidence: 99%

“…Various multiplier architectures for image processing applications have been done with imprecise compressors proposed in [12] - [14] but the overall errors are limited. The multipliers are constructed with three steps process as follows: (i) dot product generation (ii) reduction of dot product using suitable tree (iii) addition of dot product using adders [15].…”

Section: Introductionmentioning

confidence: 99%

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Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

dominic

Deepa

2021

Preprint

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The role of approximate arithmetic are involved when the processors are used for multimedia signal processing application. The impact of multiplier is very important in many processes done by these processors. The compressors are the core architecture for reduction stage if the multiplier width is increased. Later approximations are done in the compressor to limited error without affecting the signal standard. The design of scalable-split compressor is designed in this work and a counter matching method has been developed for approximation. The design of 32x32 and 16x16 multiplier with these new compressors are synthesised in 45nm Synopsis Design Compiler and shows an improvement of 25 % of Chip area and 27% power. The split-scalable architecture attempts to reduce the delay with trade-off in area and power. Mean Error Distance (MED) and Normalized Error Distance (NED) are the parameters that ensure the quality of any approximate arithmetic based design. 16-bit medical images are processed with both existing and proposed multipliers then the Peak Signal to Noise Ratio (PSNR) is compared. Finally with several input nature and targeted PSNR the best system is identified using classical machine learning model.

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Section: Multiplier Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

dominic

Deepa

2021

Preprint

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“…To reduce the error rate (probability) of the approximate multipliers, Gorantla et al investigated five scenarios to demonstrate efficient imprecise multipliers based on approximate compressors. 27 Despite reducing the error rate, these structures require high numbers of transistors, which degrades the electrical characteristics. The most efficient approximate 4:2 compressor proposed in Gorantla 27 requires 30 transistors to be realized at the transistor level.…”

Section: :2 Compressormentioning

confidence: 99%

“…27 Despite reducing the error rate, these structures require high numbers of transistors, which degrades the electrical characteristics. The most efficient approximate 4:2 compressor proposed in Gorantla 27 requires 30 transistors to be realized at the transistor level.…”

Section: :2 Compressormentioning

confidence: 99%

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Jooq

Ahmadinejad

Moaiyeri

2020

Circuit Theory & Apps

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SummaryThis study proposes two ultraefficient imprecise multipliers based on innovative 4:2 approximate compressor designs. The first proposed multiplier employs an ultracompact 8‐transistor 4:2 compressor to reduce the transistor count and energy dissipation. To improve the accuracy of the first proposed imprecise multiplier, the second multiplier also benefits from a semiaccurate 24‐transistor 4:2 approximate compressor for the high‐order bits. The 7‐nm fin field‐effect transistor (FinFET) technology, as one of the leading commercial technologies, is utilized to simulate the proposed multipliers in the environment. The simulation results indicate that the proposed imprecise multipliers show significant improvements regarding transistor count, delay, power, and power‐delay product as compared to their state‐of‐the‐art imprecise and exact counterparts. Along with the superior hardware efficiency, the MATLAB simulations demonstrate that the proposed multipliers also provide reasonable levels of accuracy. Moreover, a figure of merit (FOM) considering hardware efficiency and output quality is considered in order to evaluate the multipliers comprehensively. The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.

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“…Chang et al [23] have proposed a 4 : 2 compressor to improve energy quality efficiency in image processing with 25% error rate. Gorantla and Deepa [24] have proposed 4 : 2 and 5 : 2 compressors to reduce delay and power. Reddy et al [25] have proposed a novel design for 4 : 2 compressor with an error rate of 12.5%.…”

Section: Introductionmentioning

confidence: 99%

Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors

2020

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High speed multimedia applications have paved way for a whole new area in high speed error-tolerant circuits with approximate computing. These applications deliver high performance at the cost of reduction in accuracy. Furthermore, such implementations reduce the complexity of the system architecture, delay and power consumption. This paper explores and proposes the design and analysis of two approximate compressors with reduced area, delay and power with comparable accuracy when compared with the existing architectures. The proposed designs are implemented using 45 nm CMOS technology and efficiency of the proposed designs have been extensively verified and projected on scales of area, delay, power, Power Delay Product (PDP), Error Rate (ER), Error Distance (ED), and Accurate Output Count (AOC). The proposed approximate 4 : 2 compressor shows 56.80% reduction in area, 57.20% reduction in power, and 73.30% reduction in delay compared to an accurate 4 : 2 compressor. The proposed compressors are utilised to implement 8 × 8 and 16 × 16 Dadda multipliers. These multipliers have comparable accuracy when compared with state-of-the-art approximate multipliers. The analysis is further extended to project the application of the proposed design in error resilient applications like image smoothing and multiplication.

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Design of Approximate Compressors for Multiplication

Cited by 53 publications

References 16 publications

Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors

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