Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Abstract

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry CutBack Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits

“…2) Consistency of the estimation for 32-bit operators Table II reports the results for 32-bit inexact adder characterization. To check the consistency of the CASSIS method for this larger word-length, the CASSIS characterization has been compared to random BALL simulation with 5 million samples from [13], which is the typical inexact circuit characterization method.The chosen CCBA and ACA adders are Pareto-optimal designs for area/delay shown in the comparative study of [13]. Those adders are realistic designs to be implemented, and thus represent ideal subjects for CASSIS characterization.…”

“…The error induced by inexact operators can be evaluated with two types of approaches: 1) Analytical methods [8]- [10] mathematically expressing error statistics but the link between these statistics and the impact of the operator on the application quality metric is not straightforward. 2) Functional simulation techniques [11]- [13] simulate the inexact operator on a representative set of data and computes statistics on the approximation error. This later method is more and more employed due to the increasing amount of data generated in the Cloud or processed by data mining.…”

Adaptive simulation-based framework for error characterization of inexact circuits

“…The error induced by inexact operators can be evaluated with two types of approaches: 1) Analytical methods [13]- [16] mathematically express error statistics as the mean error distance or the error rate, but are dedicated to specific logic structures and can become really complex to implement in terms of computation time and memory for high bit-widths operators. 2) Functional simulation techniques [17]- [19] simulate the inexact operator on a representative set of data and computes statistics on the approximation error. To mimic the inexact operator behavior, bit-accurate simulations at the logic-level (BALL simulations) are required to catch the internal structure modifications of the operator.…”

“…Commonly, the error statistics are computed by simulating a given number of random inputs [17]- [19]. The quality of the statistical characterization obtained from a random sampling is highly dependent on the number of samples taken and on the chosen input distribution.…”

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

“…With the breakdown of Dennard's scaling, energy issues are becoming dominant to the development of future computing platforms, both at cloud server scale and IoT edge. At the sensor node, low-power techniques such as approximate computing [3] have been developed to trade off computation exactness for lower power consumption and increased battery life. While at the highperformance and cloud-computing scale, specialized hardware accelerators such as Field Programmable Gate Arrays (FPGA) have gained considerable interest thanks to their capability in performing massive amounts of operations in parallel with a lower energy cost [4].…”