Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits

Bonnot, J; Camus, Vincent; Desnos, Karol; Ménard, Daniel

doi:10.23919/eusipco.2018.8553451

Cited by 4 publications

(5 citation statements)

References 14 publications

(15 reference statements)

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“…In order to assess the quality of each estimate, three additional samples of five million inputs have been used to measure the deviation of the statistical estimate. Other methods have recently been proposed to improve the estimation accuracy by dynamically adjusting the number of simulation vectors [26] or by using a formal approach to analyze errors [27].…”

Section: Results and Comparisonmentioning

confidence: 99%

See 1 more Smart Citation

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Camus

Cacciotti

Schlachter

et al. 2018

IEEE J. Emerg. Sel. Topics Circuits Syst.

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This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry CutBack Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

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Section: Results and Comparisonmentioning

confidence: 99%

“…Only a handful of designs exhibits a high variation, over 5 %, mainly among high-accuracy ACA and ACAA adders. This is due to their large overlapping sub-adders inducing extremely low error rates [26]. The most critical case shows 28 % RSD for RE mean or 4 % RSD for RE max .…”

Section: Comparative Studymentioning

confidence: 99%

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Camus

Cacciotti

Schlachter

et al. 2018

IEEE J. Emerg. Sel. Topics Circuits Syst.

Self Cite

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“…In this paper, we propose a characterization method for inexact operators according to three different metrics: the mean error distance, the error rate and the upper bound of the error distance, called maximum error distance in the rest of the paper. This framework extends the preliminary work proposed in [20]. To estimate the mean error distance and the error rate, the proposed method derives the minimal number of samples to simulate, to get an accuracy on the estimation according to a given user-defined confidence interval.…”

Section: Introductionmentioning

confidence: 81%

Adaptive simulation-based framework for error characterization of inexact circuits

Bonnot

Camus

Desnos

et al. 2019

Microelectronics Reliability

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To design faster and more energy-efficient systems, numerous inexact arithmetic operators have been proposed, generally obtained by modifying the logic structure of conventional circuits. However, as the quality of service of an application has to be ensured, these operators need to be precisely characterized to be usable in commercial or real-life applications. The characterization of the error induced by inexact operators is commonly achieved with exhaustive or stochastic bit-accurate gate-level simulations. However, for high bit-widths, the time and memory required for such simulations become prohibitive. To overcome these limitations, a new characterization framework for inexact operators is proposed. The proposed framework characterizes the error induced by inexact operators in terms of mean error distance, error rate and maximum error distance, allowing to completely define the error probability mass function. By exploiting statistical properties of the approximation error, the number of simulations needed for precise characterization is minimized. From user-defined confidence requirements, the proposed method computes the minimal number of simulations to obtain the desired accuracy on the characterization for the error rate and mean error distance. The maximum error distance value is then extracted from the simulated samples using the extreme value theory. For 32-bit adders, the proposed method reduces the number of simulations needed up to a few tens of thousands points.

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“…We are not the first to investigate the necessary number of samples to bound the estimate of the error rate. In [27], an lower bound on the number of samples N f , similar to p n , is derived. Both numbers, N f and p n , depend on the actual value of er(f, f ) which is not known in advance.…”

Section: ) Performance Of the Proposed Samplingmentioning

confidence: 99%

“…Both numbers, N f and p n , depend on the actual value of er(f, f ) which is not known in advance. While in [27] this issue is addressed by iteratively approximating the error rate and the number of necessary samples alternatingly, the solution presented here is to use the improved sampling yielding a lower bound on the samples i that is independent of the actual error rate.…”

Section: ) Performance Of the Proposed Samplingmentioning

confidence: 99%

BDD-Based Error Metric Analysis, Computation and Optimization

Keszöcze

2022

IEEE Access

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Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible.In this work we extensively analyze various error metrics and approximation operations. We present methods to accelerate the computation of error metric computations by (a) exploiting structural information of the function obtained by applying the analyzed operations and (b) computing estimates of the metrics for multi-output Boolean functions represented as Binary Decision Diagrams (BDDs). We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs. The presented framework is publicly available as open-source software on GitHub.

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Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits

Cited by 4 publications

References 14 publications

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Adaptive simulation-based framework for error characterization of inexact circuits

BDD-Based Error Metric Analysis, Computation and Optimization

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