A 55-65-GHz CMOS high power amplifier (PA) is designed with the help of a spirally folded 1:2 balun. By this size-folded balun, balance-unbalanced conversion and high-power combination are accomplished concurrently. Within the internal of PA, differential signal pairs benefit simplification of inter-stage matching topologies. The designed three-stage PA offers above 16.3-dB gain from 55.1 to 65.0 GHz. It is able to deliver 17.8-dBm output referred 1-dB compression point (P 1 dB) and 22.2-dBm saturated output power (P sat) with a peak power-added efficiency of 10.9%.