Design of an NoC with on-chip photonic interconnects using adaptive CDMA links

Poddar, Soumyajit; Ghosal, Prasun; Mukherjee, Paramita; Samui, Suman; Rahaman, Hafizur

doi:10.1109/socc.2012.6398331

Cited by 6 publications

(2 citation statements)

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“…The aggregated traffic from other input channels in router and contends with dir in the output direction k F i,j X CQ [6 : 9] Forwarding probability from current channel i to four output directions CQ * X CQ [10] The estimated channel queuing time [18] The estimated source queuing time from the proposed queuing model S * X SQ [19] The estimated source service time from the proposed queuing model where g(s, d, k, i, j) is a binary indicator that returns 1 if the routing path P s,d…”

Section: Overall Svr-noc Methodologymentioning

confidence: 99%

“…Another example is the Intel 80-tile Teraflops processor [16] which is a homogeneous NoC-based CMP platform and delivers up to 1.28 TFlops of performance. Recently, photonic on-chip network based multi-core systems have also been widely studied [17,18], which further attempts to optimize the traditional metal-based interconnect performance in terms of delay and power for future SoCs with thousands PEs.…”

Section: Challenges In Computing Platform Designmentioning

confidence: 99%

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High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

Qian¹

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TABLE OF CONTENTS Title Page i Authorization Page ii Signature Page iiiAcknowledgments iv Table of Contents v List of Figures ix List of Tables xiiiAbstract xiv Therefore, fast and accurate analytical models for NoC-based multicore performance evaluation are strongly desired to better explore the design space. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations before the system is built or taped-out. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design with different design constraints and objectives. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bidirectional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel.We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with minimal energy overhead. This proposed NoC architecture exploits the selfreconfigurable bidirectional channels to increase the effective bandwidth and uses express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. From the simulation results on both synthetic traffic and real workload traces, significantly performance improvement in terms of latency and throughput can be achieved.

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Section: Overall Svr-noc Methodologymentioning

confidence: 99%