Design of an Asynchronous Microprocessor Using RSFQ-AT

Abstract

Ultra-high speed microprocessors, clocked at hundreds of Gigahertz, remain the dreams of processor designers and consumers alike. However, such processors would require designs and clocking schemes that differ radically from that of current processors. This paper discusses superconductive asynchronous processors as one alternative to mainstream processors. This asynchronous design approach requires no global clocking, which reduces the complexity of global clock distribution, clock skew and considerations for clock jitter. The design of a 4-bit asynchronous microprocessor with a simple pipeline is covered. RSFQ-AT logic and its design methodology is used, and it is shown to be well suited to large scale asynchronous circuits. We show how the RSFQ-AT design methodology simplifies and speeds up the design process. Methods for performance evaluation of this asynchronous RSFQ microprocessor is also proposed.

qCDC: Metastability-Resilient Synchronization FIFO for SFQ Logic

“…Some have argued that large-scale clock-trees will not be sufficiently robust [1], [4]. Others have proposed asynchronous or hybrid clocking strategies [5]- [8], which are expensive or require significant manual customization.…”