Design of a unified transport triggered processor for LDPC/turbo decoder

Abstract

This paper summarizes the design of a programmable processor with transport triggered architecture (TTA) for decoding LDPC and turbo codes. The processor architecture is designed in such a manner that it can be programmed for LDPC or turbo decoding for the purpose of internetworking and roaming between different networks. The standard trellis based maximum a posteriori (MAP) algorithm is used for turbo decoding. Unlike most other implementations, a supercode based sum-product algorithm is used for the check node message computation for LDPC decoding. This approach ensures the highest hardware utilization of the processor architecture for the two different algorithms. Up to our knowledge, this is the first attempt to design a TTA processor for the LDPC decoder. The processor is programmed with a high level language to meet the time-to-market requirement. The optimization techniques and the usage of the function units for both algorithms are explained in detail. The processor achieves 22.64 Mbps throughput for turbo decoding with a single iteration and 10.12 Mbps throughput for LDPC decoding with five iterations for a clock frequency of 200 MHz.

VHDL Implementation of low power turbo coded OFDM physical layer for wireless communication

“…Next, the information data is de-mapped and de-interleaved. System is being decoded by a turbo decoding process, which is carried out by a soft-decision turbo decoder [14]. This module employs the Max-map algorithm to determine the most likely transmitted sequence given the received sequence.…”

“…Moreover, the division by [8] can be substituted with a hardwired shift manner. Details of the system has been explained in [12][13][14]. Figure 5.…”

“…Recently in order to achieve high throughput of OFDM system using Turbo coding scheme [6][7][8][9][10][11] has been used. However, for turbo coding SOVA and Map [14] decoding algorithm have been developed. But, Map algorithm improved decoding speed, BER (Bit Error Rate) and system complexity.…”

“…Different architecture of FFT processor has been reported for efficient OFDM. These architecture include parallel [14] and pipelined [12] implementation such as multi-path delay feedback (MDF), singlepath delay feedback (SDF) [12],memory based [13] and memory less [12].In [13] an efficient 64 pipelined FFT engine has been introduced using single path delay feedback scheme. In [12] a memory less architecture with low space requirement has been presented.…”

Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding

“…We desire to use flexible LDPC encoding on battery-powered platforms transmitting a large amount of data wirelessly, such as portable medical imaging devices. TTA architectures have already been designed for FEC decoding, but for our application data transmission takes precedence over reception, and flexibility poses a more challenging encoding problem [4,5]. FEC schemes are usually implemented with fixed-function hardware accelerators, but this results in slow time-to-market, inflexible designs, and may consume a large area when many different accelerators are needed on the same platform.…”