Design of a Magnetic-Tunnel-Junction-Based Nonvolatile Flip-Flop  with Common-Mode Write Error Detection

Yamagishi, Goro; Natsui, Masanori; Hanyu, Takahiro

doi:10.7567/ssdm.2020.b-8-01

Cited by 1 publication

(1 citation statement)

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“…First, we clarify the vulnerability of NVFF to the stochastic behavior of MTJ devices. Thereafter, we present the details of the proposed NVFF, including circuit schematics and circuit dynamics in each operation mode, which could not be included in the previous report 28) owing to space limitations. Through the evaluation results, we demonstrate that the proposed NVFF designed using a 40 nm CMOS/MTJ-hybrid process technology can correctly detect all possible error conditions with less performance overhead.…”

Section: Introductionmentioning

confidence: 99%

Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Natsui

Yamagishi

Hanyu

2021

Jpn. J. Appl. Phys.

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Nonvolatile flip-flop (NVFF) is an important component for implementing an energy-efficient logic large-scale integration (LSI) circuit that utilizes nonvolatile memory (NVM) function of magnetic tunnel junction (MTJ) devices. NVFF must be highly reliable in data store and restore operations for nonvolatile power gating. This study proposes an NVFF that can detect arbitrary errors occurring when storing data to the embedded NVM caused by the stochastic behavior of MTJ devices. The performance evaluation results show that the proposed NVFF can detect arbitrary error conditions, including the unsupported condition in the previously proposed reliable NVFF, while maintaining comparable performance to a conventional condition in normal flip-flop operations.

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Section: Introductionmentioning

confidence: 99%