Design of a low power 4×4 multiplier based on five transistor (5-T) half adder, eight transistor (8-T) full adder & two transistor (2-T) AND gate

Abstract

In this paper, we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

A novel pipelined carry adder design based on half adder

“…The circuit diagram of the 2-T XOR gate is shown in Figure 5(a). Using the multiplexer case, the 2-bit AND gate with two transistors [25] can be found as in the Figure 5(b).…”

Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor

“…Table 1 shows truth table for the Booth encoder and figure 4 shows schematic of CCGDI based encoder circuit. The circuit shown in figure 4 consists of two quantities of three transistors based XOR gates [26] and a two transistors based GDI F1 function [5]. Compared to previous GDI encoder design [24], which was made with nine transistors and two inverters (additional four transistors), the circuit shown in figure 4 has only eight transistors.The CCGDI based Booth encoder transient responses are shown below in figure 5.…”

“…Similarly, half adders are used to accumulate two partial products of same weight. In the proposed design half adders are implemented using a 3T XOR and 2T GDI MUX [26].The transistorized schematic of full adder and half adder cell are shown in figure 14.…”