Design of a Low-Power Ultra High Speed Dynamic Latched Comparator in 90-nm CMOS Technology

Rabbi, Fazle; Das, Sajan; Hossain, Quazi Delwar; Pathan, Naqib Sad

doi:10.1109/ic4me2.2018.8465625

Cited by 8 publications

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Dynamic latch-type comparators [10][11][12][13][14] have become very attractive due to their fast regeneration time, enabled by strong positive feedback, and their zero static current consumption. Owing to their highly digital nature, these comparators are able to scale excellently into deep-submicron nodes.…”

Section: Introductionmentioning

confidence: 99%

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

View full text Add to dashboard Cite

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

show abstract