Design of a low power video decompression chip set for portable applications

Gordon, Benjamin M.; Tsern, E.K.; Meng, Tao

doi:10.1007/bf01130402

Cited by 26 publications

(14 citation statements)

References 22 publications

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“…Off-chip memories, on the other hand, represent a considerable cost in terms of power [23], [24]. Furthermore, accesses to external memories are slow, causing an impediment to the overall speed of the system.…”

Section: Motivation: a One-pass Sequential Coding Is Incompatiblementioning

confidence: 99%

Model-based rate control implementation for low-power video communications systems

Vleeschouwer

2003

IEEE Trans. Circuits Syst. Video Technol.

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This paper focuses on a major requirement of rate control (RC) algorithms when implementing a low-power video coding system: RC must be compatible with a one-pass, sequential and local processing of the frame data. This requirement prevents direct use of the most efficient RC algorithms, i.e., the ones that rely on rate-distortion (R-D) models whose parameters are computed from a pre-analysis of the input frame. The paper proposes to circumvent the problem by predicting the R-D model parameter(s) without accessing the current input frame data. It avoids the pre-analysis stage while keeping the benefit from R-D based rate control. The method is designed and illustrated for standardized and conventional hybrid coding schemes (H.26x, MPEG-x). Specifically, the mean absolute difference (MAD) of the motion prediction error, which is the key R-D model parameter, is predicted before the sequential processing of the input blocks. In order to validate the prediction, the behaviors of rate control systems using either the actual (computed) or the estimated (predicted) MAD parameter are compared.Index Terms-Low power, rate control (RC) system, video coding.

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Section: Motivation: a One-pass Sequential Coding Is Incompatiblementioning

confidence: 99%

Model-based rate control implementation for low-power video communications systems

Vleeschouwer

2003

IEEE Trans. Circuits Syst. Video Technol.

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“…Bit-lines of these DRAMs are heavily loaded with multiple storage cells [3], and so require a large energy for charging. Since one transition in a single bit-line of the 16Mbit DRAM takes as much as three orders of magnitude more power then the 1-bit adder [4], design solutions capable of minimizing the amount of signal transitions in the frame memory bit-lines are important.…”

Section: Motivationmentioning

confidence: 99%

Reducing energy consumption of video memory by bit-width compression

Moshnyaga

Inoue

Fukagawa

2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

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A new architectural technique to reduce energy dissipation of video memory is proposed. Unlike existing approaches, the technique exploits the pixel correlation in video sequences, dynamically adjusting the memory bit-width to the number of bits changed per pixel. Instead of treating the data bits independently, we group the most significant bits together, activating the corresponding group of bit-lines adaptively to data variation. The method is not restricted to the specific bit-patterns nor depends on the storage phase. It works equally well on read and write accesses, as well as during precharging. Simulation results show that using this method we can reduce the total energy consumption of video memory by 20% without affecting the picture quality.

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“…Many multimedia systems nowadays are heavily datadominated [5,6,7,8] and the on-chip memory organisation of these systems is becoming the bottleneck in power consumption. For this reason we have decided to use an SRAM memory as an IP block as a case study, where we will investigate if the energy-delay trade-off of the technology parameters can be propagated to a trade-off between memory delay (access time) and memory energy consumption per access.…”

Section: Introductionmentioning

confidence: 99%

Global interconnect trade-off for technology over memory modules to application level

Papanikolaou

Miranda

Catthoor

et al. 2003

Proceedings of the 2003 International Workshop on System-Level Interconnect Prediction

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In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach is that at future technology nodes the delay problem can be handled at the application level, so given any delay slack obtained at that level, we can exploit it to make the switching on the interconnect wires slower and thus less energy consuming. In this way, we have shown that for real-life applications the power consumption at future technology nodes can be reduced by about 34%, when compared to the option provided by the ITRS roadmap. This is achieved by, instead of using the very fast and power hungry wires, selectively using slower and thinner interconnect wires while still meeting the application real-time constraints.

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Design of a low power video decompression chip set for portable applications

Cited by 26 publications

References 22 publications

Model-based rate control implementation for low-power video communications systems

Model-based rate control implementation for low-power video communications systems

Reducing energy consumption of video memory by bit-width compression

Global interconnect trade-off for technology over memory modules to application level

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