Design of a Logarithmic Domain 2-D Convolver for Low Power Video Processing Applications

Ngo, Hau; Asari, Vijayan K.

doi:10.1109/itng.2009.287

Cited by 3 publications

(4 citation statements)

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“…It is a common approach to use approximation techniques to satisfy the computational requirement in error-tolerant applications. Although employing approximation techniques introduces errors in the calculations, it also allows a better performance in terms of the computational time, resource utilization, and energy consumption [25,26]. The binary logarithm approximation technique used in this work is based on a method of locating the index of the leading '1' bit in the binary number, which was first proposed by Mitchell [27].…”

Section: Template Matchingmentioning

confidence: 99%

Architecture Design for Feature Extraction and Template Matching in a Real-Time Iris Recognition System

et al. 2021

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Real-time support for an iris recognition algorithm is a considerable challenge for a portable system that is commonly used in the field. In this paper, an efficient parallel and pipeline architecture design for the feature extraction and template matching processes in the Ridge Energy Direction (RED) algorithm for iris recognition is presented. Several techniques used in the proposed architecture design to reduce the computational complexity while supporting a high performance capability include (i) a circle approximation method for the iris unwrapping process, (ii) a parallel design with an on-chip buffer for 2D convolution in the feature extraction process, and (iii) an approximation method for log2 and inverse-log2 conversion in the template matching process. Performance analysis shows that the proposed architecture achieves a speedup of 881 times compared to the conventional method. The proposed design can be integrated with an embedded microprocessor to realize a complete system-on-chip solution for a portable iris recognition system.

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Section: Template Matchingmentioning

confidence: 99%

Architecture Design for Feature Extraction and Template Matching in a Real-Time Iris Recognition System

et al. 2021

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“…Attempts have been made to improve Mitchell approximation by proposing several error correction circuits. These methods include Mitchell‐based methods, lookup table (LUT)‐based methods, and region‐based approaches …”

Section: Introductionmentioning

confidence: 99%

“…These methods include Mitchell-based methods, 6-9 lookup table (LUT)-based methods, [10][11][12][13][14]19,20 and region-based approaches. [15][16][17][18][19][20][21] This work concentrates on filtering (convolution) applications, where the filter weights are known and fixed. The proposed method employs Mitchell multiplier but optimizes the filter weights so that the convolution error is reduced.…”

mentioning

confidence: 99%

An efficient circuit for error reduction in logarithmic multiplication for filtering applications

Joginipelly¹,

Charalampidis

2020

Circuit Theory & Apps

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Real-time digital signal and image processing applications, such as filtering, demand high performance. Often, multiplication is one of the most timeconsuming steps of the filtering operation. Log-based multipliers have been used for improving multiplication efficiency at the expense of accuracy. The objective of the proposed work is to improve the accuracy of log-based hardware multipliers by appropriately altering the filter weights and without increasing the required resources. | INTRODUCTIONFiltering is a computationally expensive but widely used operation in image and signal processing applications including image enhancement, 1 smoothing, 2,3 and edge detection. 4 Hardware filtering implementations often have high circuitry and power consumption requirements, mainly due to the use of multipliers. Log-based multipliers convert multiplications and divisions to more efficient operators, namely, additions and subtractions, at the expense of accuracy.Mitchell 5 first proposed a method for implementing log-based multipliers using a piecewise linear approximation technique. Although the log and anti-log functions in Mitchell method are hardware efficient, they produce large average errors. Attempts have been made to improve Mitchell approximation by proposing several error correction circuits. These methods include Mitchell-based methods, 6-9 lookup table (LUT)-based methods, [10][11][12][13][14]19,20 and region-based approaches. [15][16][17][18][19][20][21] This work concentrates on filtering (convolution) applications, where the filter weights are known and fixed. The proposed method employs Mitchell multiplier but optimizes the filter weights so that the convolution error is reduced. Before presenting the proposed method, some background information about existing log-based multipliers is provided. | REVIEW OF LOGARITHMIC MULTIPLIERS | Mitchell logarithmic multiplierMitchell multiplier 5 uses a piecewise linear approximation of the log 2 (N) curve, as shown in Figure 1 for an integer N. The method is exact when N is a power of 2.The binary representation of N is Abbreviations: FF, flip flop; FPGA, field programmable gate array; IM, iterative log multiplier; LUT, lookup table; OD, operand decomposition.

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“…This PB approach has been modified in order to be area efficient but with a high memory bandwidth. In [10] an implementation of a module for 2-D Convolution based on a logarithmic approach is described. This approach aims at minimizing the power consumption.…”

Section: Introductionmentioning

confidence: 99%

An area-efficient 2-D convolution implementation on FPGA for space applications

Carlo

Gambardella

Indaco

et al. 2011

2011 IEEE 6th International Design and Test Workshop (IDT)

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The 2-D Convolution is an algorithm widely used in image and video processing. Although its computation is simple, its implementation requires a high computational power and an intensive use of memory. Field Programmable Gate Arrays (FPGA) architectures were proposed to accelerate calculations of 2-D Convolution and the use of buffers implemented on FPGAs are used to avoid direct memory access. In this paper we present an implementation of the 2-D Convolution algorithm on a FPGA architecture designed to support this operation in space applications. This proposed solution dramatically decreases the area needed keeping good performance, making it appropriate for embedded systems in critical space applications.

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Design of a Logarithmic Domain 2-D Convolver for Low Power Video Processing Applications

Cited by 3 publications

References 12 publications

Architecture Design for Feature Extraction and Template Matching in a Real-Time Iris Recognition System

Architecture Design for Feature Extraction and Template Matching in a Real-Time Iris Recognition System

An efficient circuit for error reduction in logarithmic multiplication for filtering applications

An area-efficient 2-D convolution implementation on FPGA for space applications

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