An area-efficient 2-D convolution implementation on FPGA for space applications

Carlo, Stefano Di; Gambardella, Giulio; Indaco, Marco; Rolfo, Daniele; Tiotto, Gabriele; Prinetto, P.

doi:10.1109/idt.2011.6123108

Cited by 21 publications

(11 citation statements)

References 16 publications

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“…The frequency of the clock is set to 250MHz, and the first ten pixels of the input image are set to 1,2,3,4,5,6,7,8,9,10; then the rest pixels of the image are all set to 0. The first ten elements of the convolution kernel are all set to 1, the rest are all set to 0.…”

Section: Experiments Simulation Resultsmentioning

confidence: 99%

A Hardware Design of High-throughput and Resource-saving Image Convolution

Shu¹,

Peng²,

Chen³

et al. 2017

dtcse

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Abstract. This paper proposes a hardware design of high-throughput and resource-saving image convolution. The key part of the design is consist of two aspects, buffer and computing part. For the buffer part, serial shifting register chain has been applied to buffer some of the pixels so that large number of buffer resources could be saved, thus realizing data multiplex; as for computing part, logic resource consumed is not much but time consumed for the serial convolution operation is too long. Since buffer part consumes little resource, logic duplication can be used to realize parallel design, thus accelerating the convolution operation, which reduces the time consumed largely and makes the throughput higher. In one word, this design not only accelerates the convolution operation, but also reduces the consumed resources.

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Section: Experiments Simulation Resultsmentioning

confidence: 99%

A Hardware Design of High-throughput and Resource-saving Image Convolution

Shu¹,

Peng²,

Chen³

et al. 2017

dtcse

View full text Add to dashboard Cite

show abstract

“…Since kernel factors have been internally represented through constants, 49 constant multipliers are instantiated. After that, an adder tree (similar to the one presented in [24]) adds the 49 multiplication results to produce the filtered pixel.…”

Section: Sa-femip Architecturementioning

confidence: 99%

SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications

Carlo

Gambardella

Prinetto

et al. 2015

IEEE Trans. VLSI Syst.

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Video-based navigation (VBN) is increasingly used in space applications to enable autonomous entry, descent, and landing of aircrafts. VBN algorithms require real-time performances and high computational capabilities, especially to perform features extraction and matching (FEM). In this context, field-programmable gate arrays (FPGAs) can be employed as efficient hardware accelerators. This paper proposes an improved FPGA-based FEM module. Online self-adaptation of the parameters of both the image noise filter and the features extraction algorithm is adopted to improve the algorithm robustness. Experimental results demonstrate the effectiveness of the proposed self-adaptive module. It introduces a marginal resource overhead and no timing performance degradation when compared with the reference state-of-the-art architecture.Index Terms-Field-programmable gate array (FPGA), hardware acceleration, image processing, space applications, video-based navigation (VBN). 1063-8210

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“…The arithmetic stage performs the 7 × 7 matrix convolution using the MUL/ADD tree architecture, similar to the one presented in [43]. The tree executes 49 multiplications in parallel and then adds all 49 results.…”

Section: Fpga Subsystemmentioning

confidence: 99%

A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris

Carlo

Prinetto

Rolfo

et al. 2014

EURASIP J. Adv. Signal Process.

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In order to enable the non-cooperative rendezvous, capture, and removal of large space debris, automatic recognition of the target is needed. Video-based techniques are the most suitable in the strict context of space missions, where low-energy consumption is fundamental, and sensors should be passive in order to avoid any possible damage to external objects as well as to the chaser satellite. This paper presents a novel fast shape-from-shading (SfS) algorithm and a field-programmable gate array (FPGA)-based system hardware architecture for video-based shape reconstruction of space debris. The FPGA-based architecture, equipped with a pair of cameras, includes a fast image pre-processing module, a core implementing a feature-based stereo-vision approach, and a processor that executes the novel SfS algorithm. Experimental results show the limited amount of logic resources needed to implement the proposed architecture, and the timing improvements with respect to other state-of-the-art SfS methods. The remaining resources available in the FPGA device can be exploited to integrate other vision-based techniques to improve the comprehension of debris model, allowing a fast evaluation of associated kinematics in order to select the most appropriate approach for capture of the target space debris.

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An area-efficient 2-D convolution implementation on FPGA for space applications

Cited by 21 publications

References 16 publications

A Hardware Design of High-throughput and Resource-saving Image Convolution

A Hardware Design of High-throughput and Resource-saving Image Convolution

SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications

A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris

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