Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study

Jo, Manhwee; Lee, Dong‐Wook; Han, Kyuseung; Choi, Ki‐Young

doi:10.1016/j.vlsi.2013.08.003

Cited by 7 publications

(4 citation statements)

References 22 publications

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“…However, it is not easy to map a computation-intensive Data Flow Graph (DFG) onto a Reconfigurable Cell Array (RCA), because there are many constraints. In previous studies, researchers have presented a wide range of mapping algorithms based on a variety of CGRAs [2][3][4][5][6][7][8][9][10][11][12][13][14] . Yoon et al [2] proposed the spatial mapping algorithm, known as Split-Push Kernel Mapping (SPKM), to map several applications onto resource sharing and pipelining architecture.…”

Section: Introductionmentioning

confidence: 99%

“…Ansaloni et al [7] used a novel scheduling strategy that considers both registered and unregistered communication among tiles. Lee et al [8] and Jo et al [9] introduced approaches for supporting floating-point operations for CGRAs. Kim et al [10] proposed a fast modulo routing scheduling technique for mapping 3D graphics benchmarks onto CGRAs, which improved the compilation speed.…”

Section: Introductionmentioning

confidence: 99%

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Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Chen

Wang

et al. 2021

Tsinghua Sci. Technol.

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Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints. To solve this problem, the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA. In this paper, we present a Depth-First Greedy Mapping (DFGM) algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array (RCA). Compared with level breadth mapping, the performance of DFGM is better. The percentage of maximum improvement in the use times of RCA is 33% and the percentage of maximum improvement in non-original input and output times is 64.4% (Given Discrete Cosine Transfor 8 (DCT8), and the area of reconfigurable processing unit is 56). Compared with level-based depth mapping, DFGM also obtains the lowest averages of use times of RCA, non-original input and output times, and the reconfigurable time.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Chen

Wang

et al. 2021

Tsinghua Sci. Technol.

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“…In the past, very few works have been presented where CGRAs are supporting FP operations because adding support for FP operations imposes many restrictions on the architecture. In FloRA [15] and Wave CGRA [21], integer-based PEs are combined for computing FP operations. This design results in low power consumption, but it increases the width of interconnect and degrades the output quality.…”

Section: Related Workmentioning

confidence: 99%

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

Prasad

Das

Martin

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In recent years, Coarse Grain Reconfigurable Architecture (CGRA) accelerators have been increasingly deployed in Internet-of-Things (IoT) end nodes. A modern CGRA has to support and efficiently accelerate both integer and floating-point (FP) operations. In this paper, we propose an ultra-low-power tunableprecision CGRA architectural template, called TRANSprecision floating-point Programmable archItectuRE (TRANSPIRE), and its associated compilation flow supporting both integer and FP operations. TRANSPIRE employs transprecision computing and multiple Single Instruction Multiple Data (SIMD) to accelerate FP operations while boosting energy efficiency as well. Experimental results show that TRANSPIRE achieves a maximum of 10.06× performance gain and consumes 12.91× less energy w.r.t. a RISC-V based CPU with an enhanced ISA supporting SIMD-style vectorization and FP data-types, while executing applications for near-sensor computing and embedded machine learning, with an area overhead of 1.25× only.

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“…However, to the best of our knowledge, they do not present the self-*properties that make our accelerator different from other works in the literature. Furthermore, these architectures are usually not evaluated presenting comparisons with state-of-the-art parallel embedded processors expressly conceived for efficient data processing, such as DSPs, rather exploiting soft cores [Brunelli et al 2010], general-purpose processors [Jo et al 2014], or other similar coarse-grained accelerators [Garzia et al 2009].…”

Section: Introductionmentioning

confidence: 99%

Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing

Pani

Palumbo

et al. 2015

ACM Trans. Auton. Adapt. Syst.

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Advancements in CMOS technology enable the integration of a huge number of resources on the same systemon-chip. Managing the consequent growing complexity, including fault tolerance issues in deep submicron technologies, is a hard challenge for hardware designers. Self-organization may represent a viable path toward the development of massively parallel architectures in current and future technologies. This approach is progressively more studied in multiprocessor architectures where, however, a further mind-set shift in terms of programming paradigm is required. In this article, self-organization and self-adaptiveness are exploited for the design of a coprocessing unit for array computations, supporting floating-point arithmetic. From the experience of previous explorations, an architecture embodying some principle of swarm intelligence to pursue adaptability, scalability, and fault tolerance is proposed. The architecture realizes a loosely structured collection of hardware agents implementing fixed behavioral rules aimed at the best exploitation of the available resources in whatever kind of context without any hardware reconfiguration. Comparisons with off-the-shelf very long instruction word (VLIW) digital signal processors (DSPs) on specific tasks reveal similar performance thus not paying the improved robustness with performance. The multitasking capabilities, together with the intrinsic scalability, make this approach valuable for future extensions as well, especially in the field of neuronal networks simulators.

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Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study

Cited by 7 publications

References 22 publications

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing

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