TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

Abstract

In recent years, Coarse Grain Reconfigurable Architecture (CGRA) accelerators have been increasingly deployed in Internet-of-Things (IoT) end nodes. A modern CGRA has to support and efficiently accelerate both integer and floating-point (FP) operations. In this paper, we propose an ultra-low-power tunableprecision CGRA architectural template, called TRANSprecision floating-point Programmable archItectuRE (TRANSPIRE), and its associated compilation flow supporting both integer and FP operations. TRANSPIRE employs transprecision computing and multiple Single Instruction Multiple Data (SIMD) to accelerate FP operations while boosting energy efficiency as well. Experimental results show that TRANSPIRE achieves a maximum of 10.06× performance gain and consumes 12.91× less energy w.r.t. a RISC-V based CPU with an enhanced ISA supporting SIMD-style vectorization and FP data-types, while executing applications for near-sensor computing and embedded machine learning, with an area overhead of 1.25× only.

Coarse-Grained Reconfigurable Computing with the Versat Architecture

“…Instead, two FU must be combined to implement a single-precision floating-point operation. Other CGRAs with floating-point capability have followed [25,26].…”

Low-power ultra-small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions

“…However, [31] does not focus on the three key features' comparison for the CGRAs. For understanding the performance between CGRAs and figuring out which architectures are the potential candidates for edge AI accelerators, this paper presents architectures [32][33][34][35][36][37][38][39][40][41][42] published in the recent few years for comparison. The units or reference standards are different in each architecture so that this paper consults the references and converts the various units to be standardized according to the revealed information of each architecture in Table 5-7.…”

“…Similar works are done for the rest of the architectures in Table 5-7. For exception, the area size of [34] is unable to be found out due to the lack of information. [36] does the work on an FPGA, so its core size is unable to be evaluated.…”

“…1 organizes the accelerators whose evaluation value E is in the grade of tens or hundreds from Table 2-7. [20,34,36,40] are not included in Fig. 1 because they lack the area data at the chip level.…”

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

“…The recent TRANSPIRE architecture [96] is a small 2x4 CGRA that targets near-sensor Internet of Things (IoT) use cases. Realizing the importance of variable precision floating-point computations, the TRANSPIRE architecture supports both the IEEE-754 single-precision computations and a recently proposed 8-bit format called binary8 [97].…”