Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry

Feng, Tao; Lajnef, Nizar; Chakrabartty, Shantanu

doi:10.1109/tvlsi.2015.2401037

Cited by 7 publications

(4 citation statements)

References 28 publications

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“…This work mainly concerns the design of a US-Data Down-Link embedding the proposed fully digital BPSK demodulator. Indeed, the state-of-the-art presents several modulation schemes, such as the ASK [18,19], PWM-ASK [20], OOK [19,21,22], and OOK-PM [23,24], while the BPSK demodulation has often been used for RF-powered IMDs [25][26][27][28][29][30][31].…”

Section: Starvedmentioning

confidence: 99%

A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications

2022

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Low-invasive and battery-less implantable medical devices (IMDs) have been increasingly emerging in recent years. The developed solutions in the literature often concentrate on the Bidirectional Data-Link for long-term monitoring devices. Indeed, their ability to collect data and communicate them to the external world, namely Data Up-Link, has revealed a promising solution for bioelectronic medicine. Furthermore, the capacity to control organs such as the brain, nerves, heart-beat and gastrointestinal activities, made up through the manipulation of electrical transducers, could optimise therapeutic protocols and help patients’ pain relief. These kinds of stimulations come from the modulation of a powering signal generated from an externally placed unit coupled to the implanted receivers for power/data exchanging. The established communication is also defined as a Data Down-Link. In this framework, a new solution of the Binary Phase-Shift Keying (BPSK) demodulator is presented in this paper in order to design a robust, low-area, and low-power Down-Link for ultrasound (US)-powered IMDs. The implemented system is fully digital and PLL-free, thus reducing area occupation and making it fully synthesizable. Post-layout simulation results are reported using a 28 nm Bulk CMOS technology provided by TSMC. Using a 2 MHz carrier input signal and an implant depth of 1 cm, the data rate is up to 1.33 Mbit/s with a 50% duty cycle, while the minimum average power consumption is cut-down to 3.3 μW in the typical corner.

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Section: Starvedmentioning

confidence: 99%

A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications

2022

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“…Feng et al introduced a complete system to harvest passive ultrasonic energy through conductive environment [93]. The prototype of the system was examined by Systemon-Chip (SoC) implementation in 0.5 m CMOS technology.…”

Section: Developments Of Aetmentioning

confidence: 99%

State-of-the-Art Developments of Acoustic Energy Transfer

Awal

Jusoh

Sabapathy

et al. 2016

International Journal of Antennas and Propagation

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Acoustic energy transfer (AET) technology has drawn significant industrial attention recently. This paper presents the reviews of the existing AETs sequentially, preferably, from the early stage. From the review, it is evident that, among all the classes of wireless energy transfer, AET is the safest technology to adopt. Thus, it is highly recommended for sensitive area and devices, especially implantable devices. Though, the efficiency for relatively long distances (i.e., >30 mm) is less than that of inductive or capacitive power transfer; however, the trade-off between safety considerations and performances is highly suitable and better than others. From the presented statistics, it is evident that AET is capable of transmitting 1.068 kW and 5.4 W of energy through wall and in-body medium (implants), respectively. Progressively, the AET efficiency can reach up to 88% in extension to 8.6 m separation distance which is even superior to that of inductive and capacitive power transfer.

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“…This is due to the drawbacks in the CMOS process, such as low-currentdriving capabilities, no substrate via holes, low-quality factor, and the low breakdown voltage [11], [12]. However, to reduce the cost and size, the realization of RFIC favorably needs to be implemented with the CMOS process to achieve the goal of system-on-chip (SoC) [13].…”

Section: Introductionmentioning

confidence: 99%

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

Rawat

Rajendran

Mariappan³

et al. 2022

IEEE Access

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This paper presents a bias modulation linearization technique for a 919-923 MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance (gm3) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of 1.820 x 1.771 mm 2 to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (Pout) of 27 dBm with maximum power-added efficiency (PAE) of 44.4 % and peak OIP3 of 39 dBm. A maximum linear Pout of 21 dBm with 29 % PAE is achieved at an adjacent channel leakage ratio (ACLR) of -30 dBc and 4 % error vector magnitude (EVM), satisfying the LoRa specifications.INDEX TERMS Adjacent channel leakage ratio (ACLR), bias circuit, complementary metal-oxidesemiconductor (CMOS), error vector magnitude (EVM), intermodulation distortion (IMD), long-range (LoRa), power amplifier, radio frequency power amplifier (RFPA), third-order intercept point (OIP3)

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Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry

Cited by 7 publications

References 28 publications

A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications

A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications

State-of-the-Art Developments of Acoustic Energy Transfer

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

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