Design of a bipolar 10-MHz programmable continuous-time 0.05 degrees equiripple linear phase filter

Veirman, G.A. De; Yamasaki, R.G.

doi:10.1109/4.121554

Cited by 78 publications

(20 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Of course, if a p-well CMOS process is used and MOS devices are put into p-wells connected to the respective sources, no body effect occurs and 0. Including (10) and (11) in (4) and (5), using a Maclaurin series expansion, and assuming different transconductance parameters and for the pairs M1, M2 and M3, M4, respectively, (6) can be approximated by (12) shown at the bottom of the next page, where as a function of is approximated as (13) also shown at the bottom of the next page. SPICE simulation and the calculation approach based on (13) of the voltage at node for the transconductor stage in Fig.…”

Section: B Second-order Effectsmentioning

confidence: 99%

See 1 more Smart Citation

A linear fully balanced CMOS OTA for VHF filtering applications

Szczepański

Jakusz

Schaumann

1997

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

A linear, fully balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with large dc gain and wide bandwidth is described. The approach uses a twodifferential-pair transconductor with a cross-coupled input stage together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated, dc gain enhancement is obtained without bandwidth limitation. SPICE simulations show that total harmonic distortion at 1.42 V p -p is less than 1% with dynamic range equal to 66 dB at a power consumption of 2.7 mW from a single 5-V supply. As an example, the OTA is used to design a third-order elliptic lowpass filter in the very-high-frequency range, simulated in a standard 2 m CMOS process (MOSIS).The cutoff frequency of the filter is tunable in the range of 12-50 MHz.

show abstract

Section: B Second-order Effectsmentioning

confidence: 99%

“…Design techniques based on the use of negative resistance elements were reported in the literature [9]- [12], [15], [22]- [24]. They lead to an integrator with theoretically infinite dc gain and large bandwidth.…”

Section: Introductionmentioning

confidence: 99%

A linear fully balanced CMOS OTA for VHF filtering applications

Szczepański

Jakusz

Schaumann

1997

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…The most general form of the low-pass filter transfer function is given by (18) The values for the natural frequency and of the individual biquads were chosen to satisfy a 0.05 equiripple-phase characteristic [32], where (19) The biquad order was dictated by the process of minimizing transient and dc gains from the input to the integrating nodes. Specifically, the biquads are ordered according to increasing natural frequency and quality factor [10], [33]. Referring once again to Fig.…”

Section: Resultsmentioning

confidence: 99%

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-The main problem in extending continuous-time filtering to higher frequencies is the sensitivity of high-frequency filters to analog integrator nonidealities such as finite dc gain and parasitic poles. The use of a cascode stage introduces internal nodes, and hence a nondominant pole, in the signal path. This has been overcome using a novel phase compensation scheme which does not require tuning of the compensating element, and is itself unaffected by tuning of the integrator's unity-gain frequency or quality factor. The scheme is based upon a MOS version of the "multi-tanh principle" where the linear range of a transconductor is divided between at least two unbalanced differential pairs operating in parallel. The common-source node of an unbalanced differential pair is not ac ground and the associated pole-zero pair may be harnessed to cancel the parasitic pole introduced by the cascode stage. The feasibility of the proposed design was evaluated with the fabrication of a test-chip on a 0.25 m 2.5 V standard digital CMOS process. Measurements confirm that the group delay response is flat ( 2%) over a five octave frequency range (3.5-112 MHz or 0.058-1.87 ).

show abstract

“…Design techniques based on the use of a negative loading resistance without any limitation in the bandwidth of a transconductor circuit have been reported in the literature [2], [ 17]- [19], [22], [23]. They lead to an improved integrator with theoretically infinite dc gain.…”

Section: Introductionmentioning

confidence: 99%

A CMOS transconductance element with improved DC gain and wide bandwidth for VHF applications

Szczepański

Schaumann

Pankiewicz

1996

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

The design of a fully-differential, highly linear, voltage-tunable CMOS transconductance element with improved gain performance and wide bandwidth is described. A negative resistance technique for compensation of the parasitic output resistance of the transconductor circuit is employed without requiring extra internal nodes. As a result, dc-gain enhancement is obtained without any bandwidth penalty. SPICE simulations show that for a standard 3/zm CMOS technology with a power supply of +5V, for most useful bias conditions THD is much lower than 1% for a 2VR~ts, 5MHz input sine wave; the tuning range of gm is 36#S to 265/zS. Finally the improved transconductance circuit is presented with an application to a transconductance-capacitor integrator with several tens of megahertz bandwidth.

show abstract

Design of a bipolar 10-MHz programmable continuous-time 0.05 degrees equiripple linear phase filter

Cited by 78 publications

References 13 publications

A linear fully balanced CMOS OTA for VHF filtering applications

A linear fully balanced CMOS OTA for VHF filtering applications

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A CMOS transconductance element with improved DC gain and wide bandwidth for VHF applications

Contact Info

Product

Resources

About