Design of a 9 GHz CMOS low noise amplifier using gain‐enhanced technique

Abstract

In this article, a 9 GHz low noise amplifier (LNA) using gain-enhanced technique is presented. The compact and high-gain LNA with cascode topology is implemented in a standard 0.18-lm CMOS process. The gain-enhanced technique consists of two inductors in the common gate (CG) stage of the cascode configuration. The first inductor at the source terminal in the CG stage eliminates the parasitic effects caused by the parasitic capacitances of transistors at high frequencies. Moreover, the second inductor at the gate terminal in the CG stage achieves a negative resistance making a high gain characteristic of the amplifier. Finally, the measured small signal gain, noise figure and input P 1dB at 9 GHz are 16.5 dB, 4.5 dB, and À15 dBm, respectively. The chip size of the compact LNA is 0.48 mm  0.8 mm including all testing pads.

A 2.5-GHz 8.9-dBm IIP3 current-reused LNA in 0.18-μm CMOS technology

“…The voltage shift with bulk bias can be expressed by (1), as follows: (2) where is the zero-bias threshold voltage, is the bulk source voltage, is the body effect coefficient, typically is 0.5 and is the surface potential parameter. Therefore, the derivatives are more precisely controlled by bulk bias and the corresponding range of is about six times wider than that of which means extend the range of AT biasing pointing,thus can easily identify the optimum point of the AT bias as well as maintain a stable cancellation range despite variation in Process, Voltage, Temperature (PVT).…”

“…However, it's almost impossible to achieve a strategy which can face the all desired performance. To date, two mode design strategy are adopt to achieve desired goals, one is high gain, low noise but low linearity for small desired signal with small interference and another is low gain, high linearity but high noise for large desired signal with large interference [1][2][3][4][5][6][7][8].…”

“…In the circuit level, the current-reused structure is adopted to full-fill the low power consumption and high gain, simultaneously [1] [2].…”

“…However, it's almost impossible to achieve a strategy which can face the all desired performance. To date, two mode design strategy are adopt to achieve desired goals, one is high gain, low noise but low linearity for small desired signal with small interference and another is low gain, high linearity but high noise for large desired signal with large interference [1][2][3][4][5][6][7][8].Among the variety of conventional LNA input topologies, such as resistive match common source (CS), common gate (CG), and resistive feedback CS topologies, the source inductive degeneration CS input topology shows the most promising solution. In the circuit level, the current-reused structure is adopted to full-fill the low power consumption and high gain, simultaneously [1] [2].…”

Design of Low‐Power and High‐Gain CMOS LNA with Current‐Reused Topology

“…CMOS LNAs with the advantages of low cost, low‐power consumption, and high level of integration have been extensively investigated for multigigahertz applications. Previously reported CMOS LNAs utilize cascode‐based topology for high gain or low noise considerations . These LNAs with cascode or folded‐cascode achieve high‐gain performances with low‐power consumption.…”