2017 International SoC Design Conference (ISOCC) 2017
DOI: 10.1109/isocc.2017.8368815
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Design of a 2.4-GHz 2.2-mW CMOS RF receiver front-end for BLE applications

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Cited by 3 publications
(3 citation statements)
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“…[28] and [30] have slightly lower power consumption and higher gain than this work, however, this work achieves the lowest NF. The performances of NF, conversion gain and power consumption are superior to [23], [27] and [29]. Therefore, the proposed front-end achieves the lowest NF with competitive conversion gain and power consumption power.…”
Section: Measurement Resultsmentioning
confidence: 96%
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“…[28] and [30] have slightly lower power consumption and higher gain than this work, however, this work achieves the lowest NF. The performances of NF, conversion gain and power consumption are superior to [23], [27] and [29]. Therefore, the proposed front-end achieves the lowest NF with competitive conversion gain and power consumption power.…”
Section: Measurement Resultsmentioning
confidence: 96%
“…A prototype is designed and fabricated in TSMC 55-nm CMOS technology, which achieves a measured conversion gain of 38 dB, a noise figure of 2.75dB at 2. Pin(dBm) [23]-2017 [27]-2018 [28]-2018 [29]-2017 [30]…”
Section: Resultsmentioning
confidence: 99%
“…As suggested by [12,21,26], the cascode common-source amplifier with inductive degeneration topology, shown in Figure 2, is preferred for optimal noise reduction and yet a satisfactory gain. Also, several recent reported works for BLE support the choice of this topology for ULP design [5,11,35,37,38,41,42]. In [12], the analysis is extended for the case of ULV design, observing that this type of topology is still feasible towards 0.5 V supply voltage (V DD ).…”
Section: Topology Choicementioning
confidence: 99%