2020
DOI: 10.1109/tmtt.2020.3009945
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2.4-GHz CMOS Bluetooth RF Receiver With Improved IM2 Distortion Tolerance

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Cited by 9 publications
(6 citation statements)
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“…The I/Q calibration of this work is based on the mixer’s gate bias control for the amplitude tuning, and the LO buffer’s capacitance control for the phase tuning. The proposed gate bias control circuit for the amplitude mismatch calibration can be found in more conventional sub-6 GHz RF receivers such as 0.9/1.9 GHz cellular receiver [ 26 ], 2.4 GHz Bluetooth receiver [ 27 ], and 400 MHz MedRadio receiver [ 28 ]. In addition, the same technique was also proven effective for the 28 GHz millimeter-wave RF transmitter [ 2 ].…”
Section: Implementation Resultsmentioning
confidence: 99%
“…The I/Q calibration of this work is based on the mixer’s gate bias control for the amplitude tuning, and the LO buffer’s capacitance control for the phase tuning. The proposed gate bias control circuit for the amplitude mismatch calibration can be found in more conventional sub-6 GHz RF receivers such as 0.9/1.9 GHz cellular receiver [ 26 ], 2.4 GHz Bluetooth receiver [ 27 ], and 400 MHz MedRadio receiver [ 28 ]. In addition, the same technique was also proven effective for the 28 GHz millimeter-wave RF transmitter [ 2 ].…”
Section: Implementation Resultsmentioning
confidence: 99%
“…One exception is observed at a half LO frequency near 200 MHz, where the CIR is observed to be −49 dBc. Although the MedRadio standard [ 1 ] does not clearly state this, such a limited set of exceptions would be generally accepted for the overall system operations because it can be avoided through high-level channel classification and a search process as is typically done in the Bluetooth receiver for internet-of-things (IoT) applications [ 28 , 29 ].…”
Section: Resultsmentioning
confidence: 99%
“…Thus, the differential mismatches need be minimized to suppress the IM2 distortion at the receiver output. In this design, as proposed in [ 27 , 28 ], the dc gate bias voltages V gp and V gm for the switch FET’s M 11–14 are controlled by employing a 6-bit R-2R digital-to-analog converter (DAC). The DAC needs to have a fine-tuning resolution for precise IM2 calibration, but a higher number of total bits will make the calibration process slow.…”
Section: Designsmentioning
confidence: 99%
“…It can decouple the dc offset cancellation condition and optimal gate bias condition to some extent, and thus allow the finding of the best optimal dc offset cancellation condition while minimally disturbing the dc bias condition. Due to this advantage, this technique was adopted in the author's previous sub-6 GHz CMOS transceiver designs [19,20]. The body bias voltage is precisely generated by a 6-bit voltage digital-to-analog converter (VDAC).…”
Section: Kω)mentioning
confidence: 99%