Design of 32-point mixed radix Fft processor using CSD multiplier

Kaur, Rajdeep; Singh, Tarandip

doi:10.1109/pdgc.2016.7913183

Cited by 10 publications

(4 citation statements)

References 7 publications

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“…MR techniques were also used for fast Fourier transform (FFT) pruning, which was designed to improve computational efficiency [11,12]. These algorithms have conventional applications, such as recording the flicker of voltage in smart homes [13].…”

Section: Introductionmentioning

confidence: 99%

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Shannon Entropy Loss in Mixed-Radix Conversions

Vennos

Michaels

2021

Entropy

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This paper models a translation for base-2 pseudorandom number generators (PRNGs) to mixed-radix uses such as card shuffling. In particular, we explore a shuffler algorithm that relies on a sequence of uniformly distributed random inputs from a mixed-radix domain to implement a Fisher–Yates shuffle that calls for inputs from a base-2 PRNG. Entropy is lost through this mixed-radix conversion, which is assumed to be surjective mapping from a relatively large domain of size 2J to a set of arbitrary size n. Previous research evaluated the Shannon entropy loss of a similar mapping process, but this previous bound ignored the mixed-radix component of the original formulation, focusing only on a fixed n value. In this paper, we calculate a more precise formula that takes into account a variable target domain radix, n, and further derives a tighter bound on the Shannon entropy loss of the surjective map, while demonstrating monotonicity in a decrease in entropy loss based on increased size J of the source domain 2J. Lastly, this formulation is used to specify the optimal parameters to simulate a card-shuffling algorithm with different test PRNGs, validating a concrete use case with quantifiable deviations from maximal entropy, making it suitable to low-power implementation in a casino.

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Section: Introductionmentioning

confidence: 99%

“…For example, higher radices reduce latency for memory-shared FFT architectures [14]. This additional use of MR conversions has prompted additional research on MR [12,15,16].…”

Section: Introductionmentioning

confidence: 99%

Shannon Entropy Loss in Mixed-Radix Conversions

Vennos

Michaels

2021

Entropy

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“…In addition to fulfilling these three major aspects of floating point multiplier, CSD technique is proven to be useful in implementing multiplier with reduced complexity, because the cost of multiplication may be a direct function of the amount of non-zero bits within the multiplier [15]. The learning of the digit-slicing method has been explained in [16] for the digital filters. Digit-slicing FFT hardware design and implementation is discussed in [17].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

Padma¹

2021

TURCOMAT

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There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butterfly structures for the reduction of complex multipliers presented. Implementations of 32 bit floating point multiplier and floating point adder are presented by using single precision and compare the synthesis results with conventional system. In order to reduce the error we used floating point arithmetic for the butterfly structure. Energy efficient multiplier based on modified booth algorithm is used in radix-2 butterflies. By adopting this architecture the FFT/IFFT implementation using Xilinx FPGA Vertex-7 will improve the 25% logic utilization and the reduction in space utilization. Using arithmetic reduction the power delay product for radix 2 butterfly is reduced by 2.5% compared to normal implementation.

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“…From the above property, the SD number representation and its arithmetic are suitable for high-precision scienti¯c computation, real-time signal processing, etc. [13][14][15][16][17][18] Moreover, several researches on arithmetic circuit using the SD number representation on FPGA [19][20][21][22][23][24][25][26] are reported. The main disadvantage of the SD number arithmetic is that many logic elements are required when these algorithms are realized on a logic circuit.…”

Section: Introductionmentioning

confidence: 99%

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Tanaka

Suzuki

Wei

2019

J CIRCUIT SYST COMP

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Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

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Design of 32-point mixed radix Fft processor using CSD multiplier

Cited by 10 publications

References 7 publications

Shannon Entropy Loss in Mixed-Radix Conversions

Shannon Entropy Loss in Mixed-Radix Conversions

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

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