An emerging beyond "CMOS"-based technology, named as "QCA spin technology," is utilized in this study to design a hybrid crossover-based 3D addersubtractor using modified reversible universal gate (RUG) and reversible 3-input Thapiyal gate (TS-3). The occupied area, latency, and power dissipation of our proposed design is optimized in our work compared to previously published addersubtractor designs due to the advancement of used above reversible gates in multilayer QCA spin platform with a collaboration of coplanar wire crossing and multilayer wire crossing. QCA designer software is mainly used in this work to simulate the physical layout architecture of our proposed formation, and this simulated outputs help to calculate the latency and the output strength of presented design. The area occupation and cell count can be achieved by selecting the layout design, and power dissipation is calculated over here based on switching time, electron tunneling rate, and the cell count.