Design methodology for fault tolerant ASICs

Petrović, Vladimir; Ilic, Marko; Schoof, Gunter; Stamenković, Zoran

doi:10.1109/ddecs.2012.6219014

Cited by 11 publications

(5 citation statements)

References 12 publications

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“…Finally, the zero suppression circuitry combines the parallel outputs of the cluster detection, and reduces the data flow by skipping non-hit clusters. SEU mitigation techniques [9] were implemented to improve radiation hardness of critical blocks (figure 6). Most critical units like internal configuration storage registers, reset management and the sequencer were protected using triple modular redundancy with 70 µm distance between modules.…”

Section: Digital Signal Processing and Zero Suppression Unitmentioning

confidence: 99%

Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

Flouzat¹,

Değerli²,

Guilloux³

et al. 2015

J. Inst.

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In the framework of the ALICE experiment upgrade at HL-LHC, a new forward tracking detector, the Muon Forward Tracker (MFT), is foreseen to overcome the intrinsic limitations of the present Muon Spectrometer and will perform new measurements of general interest for the whole ALICE physics. To fulfill the new detector requirements, CMOS Monolithic Active Pixel Sensors (MAPS) provide an attractive trade-off between readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This technology has been chosen to equip the Muon Forward Tracker and also the vertex detector: the Inner Tracking System (ITS). Since few years, an intensive R&D program has been performed on the design of MAPS in the 0.18 µm CMOS Image Sensor (CIS) process. In order to avoid pile up effects in the experiment, the classical rolling shutter readout system of MAPS has been improved to overcome the readout speed limitation. A zero suppression algorithm, based on a 3 by 3 cluster finding (position and data), has been chosen for the MFT. This algorithm allows adequate data compression for the sensor. This paper presents the large size prototype PIXAM, which represents 1/3 of the final chip, and will focus specially on the zero suppression block architecture. This chip is designed and under fabrication in the 0.18 µm CIS process. Finally, the readout electronics principle to send out the compressed data flow is also presented taking into account the cluster occupancy per MFT plane for a single central Pb-Pb collision.

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Section: Digital Signal Processing and Zero Suppression Unitmentioning

confidence: 99%

Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

Flouzat¹,

Değerli²,

Guilloux³

et al. 2015

J. Inst.

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“…The proposed SEL protection switch is shown in Figure 1. It is an improved version of the switch presented in [23] and [24]. The main task of this circuit is to switch off the power supply in case of the excessive supply current.…”

Section: Latchup Protectionmentioning

confidence: 99%

“…It means that the redundancy is lost during the latchup protection. However, modifications of the voter feed-back logic are necessary since the standard self-voting DMR circuit is very sensitive to a SET hitting the flip-flop data input near the active clock edge [23].…”

Section: Self-voting Dmr With Latchup Protectionmentioning

confidence: 99%

Fault-tolerant ASIC: Design and implementation

2013

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The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

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“…Hence, although DMR approaches are not capable of error correction, they are widely used for their lower area overhead and power consumption. In addition, their error detection property, improves the robustness of a component against failures (Petrovic et al, 2012). In crucial tasks where the reliability is of great importance, such as in aerospace applications, the designers have to accept the area and power overhead to increase the reliability.…”

Section: Introductionmentioning

confidence: 99%

“…Many different DMR and TMR approaches have been proposed. Petrovic et al, (Petrovic et al, 2012), have proposed a novel self-voting DMR approach which freezes the output when detects a transient error on one of the modules outputs. Another DMR approach is also suggested in (Teifel, 2008) which guarantees the same level of Single-Event Transient (SET) protection as a TMR approach for SET pulses with less width than a constant value.…”

Section: Introductionmentioning

confidence: 99%

Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

Ansari

Mahani²,

Mohammadi³

2016

COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose To increase protection level against transient faults, circuit designers usually take advantage of redundant structures like Triple Modular Redundancy (TMR). Since redundancy compel a significant power overhead, proposing a low power fault tolerant technique in digital circuits is the main objective of this research work. Design/methodology/approach In order to moderate power consumption, we use a dual to triple modular redundancy. In fact, we put one of the modules in a TMR system in sleep mode while the other two operating modules are producing the same outputs. Once a mismatch is detected, the third one exits the sleep mode and the dual modular redundancy (DMR) approach turns into a conventional TMR. Also a novel stoppable clock generator is proposed to handle the sleep mode of the third module. Finally, a new three-input majority voter, compatible with our proposed technique, is presented. Findings Power analysis of combinational circuit benchmarks, ISCAS85, and ISCAS89 as sequential circuit benchmarks are depicted. Simulation results show the power reduction of up to 30% in comparison with the conventional modular redundancy approach. Originality/value Since modular redundancy is the most effective and the most well-known fault tolerant approach which is widely used in reliable circuits designs, it is important to reduce its power consumption. In this paper configuring the sleep mode operation of a circuit and stoppable clock generator lead to a new TMR technique in which the power consumption is strongly reduced.

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Design methodology for fault tolerant ASICs

Cited by 11 publications

References 12 publications

Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

Fault-tolerant ASIC: Design and implementation

Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

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