Design Margin Methodology for DDR Interface

Sarkar, S.; Brahme, Amit; Chandar, G. Subash

doi:10.1109/epep.2007.4387151

Cited by 9 publications

(2 citation statements)

References 3 publications

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“…It also includes voltage and timing uncertainty models that help relate parameters that affect power and timing. Voltage and timing budgets are traditionally used by interface designers to begin building components of the interface [2], [4], [41], [49] and budget the eye diagram between the DRAM, interconnect, and the controller, as shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

Jouppi

Kahng

Muralimanohar

et al. 2015

IEEE Trans. VLSI Syst.

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In this paper, we describe CACTI-IO, an extension to CACTI that includes power, area, and timing models for the IO and PHY of the OFF-chip memory interface for various server and mobile configurations. CACTI-IO enables design space exploration of the OFF-chip IO along with the dynamic random access memory and cache parameters. We describe the models added and four case studies that use CACTI-IO to study the tradeoffs between memory capacity, bandwidth (BW), and power. The case studies show that CACTI-IO helps to: 1) provide IO power numbers that can be fed into a system simulator for accurate power calculations; 2) optimize OFF-chip configurations including the bus width, number of ranks, memory data width, and OFF-chip bus frequency, especially for novel buffer-based topologies; and 3) enable architects to quickly explore new interconnect technologies, including 3-D interconnect. We find that buffers on board and 3-D technologies offer an attractive design space involving power, BW, and capacity when appropriate interconnect parameters are deployed.Index Terms-CACTI, CACTI-IO, dynamic random access memory (DRAM), IO, memory interface, power and timing models.

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Section: Introductionmentioning

confidence: 99%

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

Jouppi

Kahng

Muralimanohar

et al. 2015

IEEE Trans. VLSI Syst.

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show abstract

“…It also includes voltage and timing uncertainty models that help relate parameters that affect power and timing. Voltage and timing budgets are traditionally used by interface designers to begin building components of the interface [1], [3], [34], [42] and budget the eye diagram between the DRAM, interconnect, and the controller as shown in Figure 2. The Eye Mask represents the portion of the eye budgeted for the Rx (receiver).…”

Section: Introductionmentioning

confidence: 99%

Cacti-Io

Jouppi

Kahng

Muralimanohar

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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We describe CACTI-IO, an extension to CACTI [4] that includes power, area and timing models for the IO and PHY of the off-chip memory interface for various server and mobile configurations. CACTI-IO enables design space exploration of the off-chip IO along with the DRAM and cache parameters. We describe the models added and three case studies that use CACTI-IO to study the tradeoffs between memory capacity, bandwidth and power.The case studies show that CACTI-IO helps (i) provide IO power numbers that can be fed into a system simulator for accurate power calculations, (ii) optimize off-chip configurations including the bus width, number of ranks, memory data width and off-chip bus frequency, especially for novel buffer-based topologies, and (iii) enable architects to quickly explore new interconnect technologies, including 3-D interconnect. We find that buffers on board and 3-D technologies offer an attractive design space involving power, bandwidth and capacity when appropriate interconnect parameters are deployed.

show abstract