Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA

Kamaleldin, Ahmed; Mohamed, Ahmed Shawky; Nagy, Ahmed; Gamal, Youssef; Shalash, Ahmed F.; Ismail, Yehea; Mostafa, Hassan

doi:10.1109/iscas.2017.8050456

Cited by 15 publications

(10 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Xilinx presents several IP cores that can be used for the interfacing of Xilinx's ICAP primitive with the user system design. Xilinx ICAP controller's main functionality is enabling the embedded microprocessors such as micro blaze and ARM processors to have access to the configuration memory [20]. ICAP is a Xilinx FPGA hard macro that allows direct access to the configuration memory in read and write modes.…”

Section: Xilinx Axi-hwicap Controllermentioning

confidence: 99%

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

2021

View full text Add to dashboard Cite

IoT technology is evolving at a quick pace and is becoming an important part of everyday life. Consequently, IoT systems hold large amounts of data related to the user of the system that is vulnerable to security breaches. Thus, data collected by IoT systems need to be secured efficiently without affecting the IoT systems’ performance and without compromising security as well. In this paper, a high-performance dynamic security system is introduced. The system makes use of the ZedBoard’s dynamic partial reconfiguration capability to shift between three distinct cipher algorithms: AEGIS, ASCON, and DEOXYS-II. The switching between the three algorithms is performed using two different techniques: the algorithm hopping technique or the power adaptive technique. The choice of which technique to be used is dependent on whether the system needs to be focused on performance or power saving. The ciphers used are the CAESAR competition finalists that achieved the greatest results in each of the three competition categories, where each cipher algorithm has its own set of significant characteristics. The proposed design seeks to reduce the FPGA reconfiguration time by the application of LZ4 (Lempel-Ziv4) compression and decompression techniques on the ciphers’ bitstream files. The reconfiguration time decreased by a minimum of 38% in comparison to the state-of-the-art design, while the resource utilization increased by approximately 2%.

show abstract

Section: Xilinx Axi-hwicap Controllermentioning

confidence: 99%

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

2021

View full text Add to dashboard Cite

show abstract

“…FEC module [7] is used to correct errors on the receiving end in wireless communication. Such errors must have occurred because the medium between Transmitter and receiver has interference, noise or various other impairments.…”

Section: Fec (Forward Error Correction)mentioning

confidence: 99%

“…Generate random BPSK Modulated symbols [10] +1,-1. Encode using convolutional encoder with a half rate generator polynomial [7,5]…”

Section: Viterbi Decoding Stepsmentioning

confidence: 99%

A New Model Based Design of SDR for Reducing Error Transmission

2019

IJITEE

View full text Add to dashboard Cite

In this paper, a SDR model-based concept approach to the implementation of SDR digital communication. The wireless communication systems are a popular prototyping platform. We propose to create a secure, private wireless channel between two SDR (Software Defined Radio) terminals. It is not the safest option to transfer sensitive data wirelessly via the web. We, therefore, offer an alternative short distance use of the internet for the transmission of secured data. We have implemented different modulation and encoding methods and we have compared their performance with Matlab with the main aim of reducing the BER bit error rate. An entire digital communication system is installed and validated via on-air demonstration that includes a transmitter with an encoder and a receiver. For hardware efficiency, synchronization algorithms including offset stage, offset carrier frequency and recovery time are also optimized.

show abstract

“…Xilinx Virtex 5 FPGAs have different configuration modes, external and internal. 22 A study compares the different configuration modes for Xilinx Virtex FPGAs 5 is presented in Hassan et al, 23 another comparison targeting internal partial reconfiguration controllers for Xilinx Zynq FPGA is presented in Kamaleldin et al 24 JTAG is an external configuration mode with maximum throughput 8.25 MBps 22 is used for the simplicity of the design. The initial configuration time using JTAG = the initial configuration file size/maximum throughput of the JTAG = 3.8 MB/8.25 MBps = 460 millseconds.…”

Section: Time Overheadmentioning

confidence: 99%

Towards the implementation of Multi‐band Multi‐standard Software‐Defined Radio using Dynamic Partial Reconfiguration

Sadek

Mostafa

Nassar

et al. 2017

Int J Communication

Self Cite

View full text Add to dashboard Cite

Summary The vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine‐grained block level, in implementing a baseband physical layer processing module for software‐defined radio (SDR) chain that supports 3G, long‐term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run‐time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5‐LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long‐term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.

show abstract

Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA

Cited by 15 publications

References 9 publications

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

A New Model Based Design of SDR for Reducing Error Transmission

Towards the implementation of Multi‐band Multi‐standard Software‐Defined Radio using Dynamic Partial Reconfiguration

Contact Info

Product

Resources

About