Design Guidelines for Sub-12 nm Nanowire MOSFETs

Salmani-Jelodar, Mehdi; Mehrotra, Saumitra Raj; Ilatikhameneh, Hesameddin; Klimeck, Gerhard

doi:10.1109/tnano.2015.2395441

Cited by 37 publications

(27 citation statements)

References 17 publications

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“…Neglecting holes means that band-to-band tunneling is ignored in these simulations. This effect is negligible in devices, whose source-to-drain voltage (V DS ) is smaller than the band gap of the channel material [15,16]. DG device specifications are in correspondence to the ITRS table data for the 2015 node (Fig.…”

mentioning

confidence: 72%

“…Gate leakage results from the tunneling of electrons through the potential barrier between the gate and the channel. I Gate is exponentially related to the oxide thickness (T OX = T SiO2 +T high−k ) and oxide effective mass [3,16]. (Fig.…”

Section: Methodsmentioning

confidence: 99%

“…3-C). SS depends on the current at sub-threshold region, which is controlled by the electrostatics and the gate leakage [16]. Thinning T OX enhances the gate control, which improves SS until I Gate becomes comparable to I OFF .…”

Section: Methodsmentioning

confidence: 99%

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Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Salmani-Jelodar

Ilatikhameneh

Kim

et al. 2016

IEEE Trans. Nanotechnology

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A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as SiO2, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this letter, the effects of high-k oxides on double-gate (DG) MOSFET with the gate length under 20 nm are studied. We find that there is an optimum physical oxide thickness (TOX) for each gate stack, including SiO2 interface layer and one high-k material. For the same EOT, Al2O3 (k=9) over 3Å SiO2 provides the best performance, while for HfO2 (k=20) and La2O3 (k=30), SiO2 thicknesses should be 5Å and 7Å, respectively. The effects of using high-k oxides and gate stacks on the performance of ultra-scaled MOSFETs are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.

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mentioning

confidence: 72%

Section: Methodsmentioning

confidence: 99%

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Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Salmani-Jelodar

Ilatikhameneh

Kim

et al. 2016

IEEE Trans. Nanotechnology

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“…he gate---all---around (GAA) silicon nanowire transistors (NWT) have the potential to keep Moore's law continuing beyond the 7 nm mark [1][2][3]. One of the major reasons is that GAA design provides the best electrostatic integrity in comparison to all other different transistor architectures and therefore the best gate control over the channel [4,5].…”

Section: Intoductionmentioning

confidence: 99%

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Al-Ameri

Wang

Georgiev

et al. 2015

2015 IEEE Nanotechnology Materials and Devices Conference (NMDC)

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Abstract-This work investigates the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six various cross-section shapes. However all devices in the crosssectional area is kept constant in order to provide fair comparison between them. Additionally we expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we were able to obtain correlation between the mobile charge distributions in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such nano-scale dimensions.

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“…he gate-all-around (GAA) silicon nanowire transistors (NWT) have the potential to extend Moore's law beyond the 7nm mark [1][2][3]. One of the major reasons being that the GAA design provides the best electrostatic integrity in comparison to all other transistors architectures and therefore the best gate control over the channel [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

Al-Ameri

Georgiev

Sadi

et al. 2017

Solid-State Electronics

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Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit. Solid-State Electronics, 129, pp. 73-80. (doi:10.1016/j.sse.2016 This is the author's final accepted version.There may be differences between this version and the published version. You are advised to consult the publisher's version if you wish to cite from it.http://eprints.gla.ac.uk/133442/ Deposited on: 04 January 2017 Enlighten -Research publications by members of the University of Glasgow http://eprints.gla.ac.uk 1  Abstract-In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <110> and <100> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90 o on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5nm, 6nm, 7nm and 8nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

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Design Guidelines for Sub-12 nm Nanowire MOSFETs

Cited by 37 publications

References 17 publications

Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

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