Seventh International IEEE Conference on VLSI Multilevel Interconnection
DOI: 10.1109/vmic.1990.127916
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Design guidelines for deep-sub-micrometer interconnections

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“…In ultralarge scale integration (ULSI) technology multilevel interconnections are required, where a problem may arise with a large RC delay time resulting from large parasitic capacitance of interlayer dielectrics [1]. One way to reduce the dielectric constant is to replace the silicon dioxide (SiO 2 ) by fluorinated silicon oxide (SiOF) [2,3].…”
Section: Introductionmentioning
confidence: 99%
“…In ultralarge scale integration (ULSI) technology multilevel interconnections are required, where a problem may arise with a large RC delay time resulting from large parasitic capacitance of interlayer dielectrics [1]. One way to reduce the dielectric constant is to replace the silicon dioxide (SiO 2 ) by fluorinated silicon oxide (SiOF) [2,3].…”
Section: Introductionmentioning
confidence: 99%