Design FPGA-Based Fuzzification Algorithm for Model-free Control Techniques

Piltan, Farzin; Rahmani, Maryam; Mahmoudi, Omid; Esmaeili, Meysam; Tayebi, Mohammad A.; Piltan, Mahsa; Cheraghi, Hamid

doi:10.14257/ijhit.2016.9.8.22

Cited by 1 publication

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“…Once the design is set, hardwired chips are produced for faster performance. Field Programmable Gate Arrays (FPGAs) are divided into two major categories [8][9][10]:…”

Section: Design Spartan Fpga Based Pd Controllermentioning

confidence: 99%

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Design SPARTAN FPGA-Based PD Controller for FOD Systems

Sahamijoo¹,

Piltan²,

Ghiasi³

et al. 2016

IJSH

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It goes without saying that, there is quite a diverse mixture of the linear controller. Nevertheless, I assume the most famous would probably be Proportional Integral (PI) controller. The things with PI controller are that most of PI controllers are reduction the error. As well as PI controllers, another kind of linear controller worth mentioning could be Proportional Derivative (PD) controller and the unique characteristic of PD controller is that PD controllers are high speed and independent of system's dynamic modeling. In addition, there are the usual things like PID controllers and PI2D controllers. The main objective of this paper designs a minimum delay proportionalderivative (PD) controller to the control of first order delay (FOD) system. First order delay system has delay time about 4 seconds in certain and about 19 seconds in limited uncertain condition. To improve the flexibility, design high-speed and low-cost controller, the micro-electronic device (FPGA-Based) controller is used in this research. The proposed design is 30-bits FPGA-based controller for inputs and 35-bits for output. In this research, the maximum frequency is 63.629 MHz and the minimum period is 15.716 ns, the minimum input arrival time before the clock is 4.362 ns and the maximum output required time after clock is19.727 ns. In this algorithm, the delay time for the derivative algorithm is 15.526 ns which 87.8% is a logic delay and 12.2% is route delay.

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“…Once the design is set, hardwired chips are produced for faster performance. Field Programmable Gate Arrays (FPGAs) are divided into two major categories [8][9][10]:…”

Section: Design Spartan Fpga Based Pd Controllermentioning

confidence: 99%

“…FPGAs Xilinx Spartan 3E families are one of the most powerful flexible Hardware Language Description (HDL) programmable IC's. To have the high speed processing FPGA based sliding mode controller in Xilinx ISE 9.1 is designed and implemented [9][10][11][12].…”

Section: Design Spartan Fpga Based Pd Controllermentioning

confidence: 99%