Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Abstract

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method. INTRODUCTIONAccording to the recent advance of semiconductor process technology, the circuit densities on LSI are growing and the automatic test design becomes more important. Because the automatic test pattern generation (ATPG) for a sequential circuit is difficult in general, a design for testability (DFT) must be applied to obtain high fault efficiency. The full scan design method [1,2] is one of popular DFT methods, so far. In the full scan design method, all flip-flops (FFs) are replaced with scan FFs. A scan FF is equivalent to a primary input and a primary output at the test mode. In the scan design method, ATPG can be performed for the portion of the circuit excluding the scan path, which is the kernel circuit. Since the kernel circuit of the full scan design LSI is a combinational one, a combinational ATPG algorithm can be applied to it and it can obtain high fault efficiency.Test application time by the scan design method is the product of the test length of an automatic test equipment (ATE) of the formula (1) and the clock period of the ATE. TL = (TP +1) × MSL + TP …(1)In the formula(1), TL is test length of an ATE, TP is the number of test patterns of the kernel circuit and is called the ATPG patterns, MSL is the maximum number of scan FFs on one scan paths and is called the maximum scan path length.As the increasing number of the external pins on LSI boundary is slower than the increase of the size of an LSI, the number of scan FFs on a scan path connected to the external pins increases relatively. Consequently, the full-scan-design test application time becomes longer. The formula (1) shows that the test length of a scan design method can be shortened by shortening the maximum scan path length and/or by reducing the number of ATPG patterns.In this paper, three DFT strategies are proposed in order to reduce test application times as follows:(1) DFT strategy1: applies the full scan design method with test point insertions to an LSI. (2) DFT strategy2: applies the partial scan design method to an LSI. (3) DFT strategy3: applies the partial scan design method with test point insertions to an LSI. The next section explains the motivation of this research. In section 3, the three DFT strategies are proposed. The effectiveness of the strategies by applying them to practical LSIs are showed in section 4. The conclusion and our future works are described in section 5. MOTIVATIONThe road map of ITRS [3] predicts that the number of gates increases at a rate of about 40% per year, and the number of externa...

Test cost reduction for logic circuits: Reduction of test data volume and test application time

“…Test point insertion techniques [13][14][15] are effective for achieving high fault coverage with a small number of test vectors. They are also effective for increasing fault coverage in logic BIST [16].…”