Design for testability of a 32-bit microprocessor-the TX1

Nozuyama, Y.; Nishimura, A.; Iwamura, Jun

doi:10.1109/test.1988.207795

Cited by 16 publications

(1 citation statement)

References 3 publications

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“…Since the test circuits are reconfigurable, this can be useful in testing a family of processors or DSPs in high-volume manufacturing. Using this technique, the built-in-self-test (BIST) overhead in silicon can be reduced below 5% (LFSR/MISR boundary scan elements/hold latches can be moved to the TFT layer), compared to 15% BIST overhead in conventional design such as the Intel Pentium Pro processor [Nozuyama et al 1988]. …”

Section: Test Practice: Offline Testmentioning

confidence: 99%

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

Bansal²,

Ghosh

et al. 2008

J. Emerg. Technol. Comput. Syst.

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This article presents a holistic hybrid design methodology for low-power, low-cost, testable digital designs using low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs). An alternate scaling rule under low thermal budget (due to flexible substrate) is developed to improve the performance of TFTs in the presence of process variation. We demonstrate that LTPS TFTs can be further optimized for ultralow-power subthreshold operation with performances comparable to contemporary single-crystal silicon-on-insulator (c-Si SOI) devices after process optimization. The optimized LTPS TFTs with high current drivability and less variability can comprise a promising low-cost option to augment Si CMOS technology, opening up a plethora of new hybrid 3D applications. We illustrate one such application: IC testing. Testing of complex VLSI systems is a prime concern due to design cost of DFT circuits, area/delay overheads, and poor test confidence. To harness the benefits of TFT technology, a novel low-power, process-tolerant, generic, and reconfigurable test structure designed using LTPS TFTs is proposed to reduce the test cost, as well as to improve diagnosability and verifiability, of complex VLSI systems. Due to proper optimization of TFT devices, the proposed test structure consumes low power but operates with reasonable performance. Furthermore, the test circuits do not consume any silicon area because they can be integrated on-chip using 3D technology. Since the test architecture is reconfigurable, this This research was supported by DARPA. 13:2• J. Li et al.eliminates the need to redesign built-in-self-test (BIST) components that may vary from one processor generation to another. We have developed test structures using 200nm TFT devices and evaluated them on designs implemented in 130nm bulk CMOS. For circuit simulations, we have developed a SPICE-compatible model for TFT devices. The BIST components designed using the test structures operate at 0.8-4.3 GHz (compared to 8.2 GHz in bulk CMOS) with low power consumption. The enhanced scan cells partially implemented in TFT (3D hybrid design) consume ∼24% less power and ∼15-20% less area of Si die compared to conventional bulk-Si design (2D planar design), with minimal delay overhead.

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Section: Test Practice: Offline Testmentioning

confidence: 99%