Design for manufacturability for fabless manufactuers

Radojcic, Riko; Perry, D.; Nakamoto, Mark

doi:10.1109/mssc.2009.933437

Cited by 8 publications

(5 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Further modeling and characterization of the stress impact on MOS devices is needed to gain a better insight and asses the severity of this issue. To avoid large keep out areas (areas in which no devices are placed) and increase cost of the use of 3-D TSV technology, models and tools to design for TSV impact on devices are recommended [20].…”

Section: Mechanical Issues and Considerationsmentioning

confidence: 99%

Design issues and considerations for low-cost 3D TSV IC technology

Plas

Limaye²,

Mercha³

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

Self Cite

View full text Add to dashboard Cite

Section: Mechanical Issues and Considerationsmentioning

confidence: 99%

Design issues and considerations for low-cost 3D TSV IC technology

Plas

Limaye²,

Mercha³

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

Self Cite

View full text Add to dashboard Cite

Section: Mechanical Issues and Considerationsmentioning

confidence: 99%

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Plas

Limaye

Loi

et al. 2011

IEEE J. Solid-State Circuits

Self Cite

240

View full text Add to dashboard Cite

“…Similar threshold shift has been measured for p-type devices with longer channel lengths. To avoid large keep out areas (areas in which no devices are placed) and increase cost of the use of 3D TSV technology, models and tools to design for TSV impact on devices are recommended [9]. …”

Section: Tsv Proximity and Impact On Device Performancementioning

confidence: 99%

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions

Plas

Thijs

Linten

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

View full text Add to dashboard Cite

We describe the design challenges for a low-cost 130nm 3D CMOS technology with 5µm diameter at 10µm pitch Cu-TSV. We investigate electrical, thermal and thermomechanical issues encountered in 3D. The electrical yield and ESD of TSVs is reviewed and designers are advised how to ensure yield and reliability. For thermal and thermomechanical we'll indicate based on experimental characterization, the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow which leverages information captured by smart samples. Introduction 3D TSV (through silicon via) technologies promise increased system integration at lower cost and reduced footprint [1]. Many flavours of 3D technologies have recently been introduced in application areas such as DRAM stacking [2], imagers [3][4] and SSDs (Solid-StateDrives) [5].Figure 1 Process flow of low-cost 3D Cu TSV technology,Cu TSV are processed after FEOL and before BEOL, next wafers are thinned and dies singulated. Stacking is performed die to wafer with simultaneous Cu-Cu thermo-compression to create both mechanical and electrical connections. In this paper we propose a 3D stacked IC (3D-SIC) technology that leverages existing IC foundry infrastructure to fabricate through silicon vias (TSVs) after the FEOL processing and prior to BEOL processing [6] ( Figure 1). The TSVs are patterned in the CMOS IC after the PMD layer deposition. For the test vehicle reported in this paper, TSVs were fabricated with 5 µm diameter and a minimum pitch of 10 µm. After the TSV is etched, an isolation layer of SACVD O3 TEOS layer is deposited followed by the metallization of the TSV with a PVD Ta barrier/ PVD Cu seed and ECD via fill. The Cu overburden is then polished with a CMP step and the wafers go through the standard BEOL process. To enable interconnections using TSVs, the wafer is then mounted on a temporary carrier wafer and thinned down to ~25 µm with rough grinding, fine grinding and CMP to expose the TSVs from the backside of the wafer. The TSVs are exposed further to a height of ~700 nm with a Si recess etch process. Next the wafers are diced and individual dies are stacked on the landing wafer with a collective hybrid bonding process in a die-to-wafer approach [7]. This approach reduces the cycle time by the parallel processing of the relatively long Cu-Cu thermocompression step and the die-to-wafer configuration allows the selection of Known Good Die (KGD) prior to stacking. Using this technology in this paper we review the electrical, thermal and thermo-mechanical challenges and solutions. In next subsection we address the electrical issues (TSV characteristics and ESD), in the following section we address thermal and thermo-mechanical. Electrical TSV Characteristics and ESD DC Resistance and low frequency capacitance are fundamental electrical parameters of TSVs [8]. We measured the TSV resistance between the top of the TSV and the landing pad since it provides information on the quality of the vertical electric...

show abstract

Design for manufacturability for fabless manufactuers

Cited by 8 publications

References 12 publications

Design issues and considerations for low-cost 3D TSV IC technology

Design issues and considerations for low-cost 3D TSV IC technology

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions

Contact Info

Product

Resources

About