Design criteria for shoot-through elimination in Trench Field Plate Power MOSFET

Nishiwaki, Tatsuya; Hara, T.; Kaganoi, Keisuke; Yokota, M.; Hokomoto, Yoshitaka; Kawaguchi, Yusuke

doi:10.1109/ispsd.2014.6856056

Cited by 15 publications

(4 citation statements)

References 3 publications

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“…However, a dynamic avalanche occurs when the internal snubber has a large value of R S . [26][27][28] Reference 26 analyzed a shoot-through in an FP-MOSFET. When the electrical potential of FP increases with large R S during reverse recovery periods, the blocking voltage of FP-MOSFET decreases.…”

Section: Simulation Results Of Dynamic Avalanchementioning

confidence: 99%

Improvement of Q _rr –I _DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Kobayashi¹,

Nishiwaki²,

Goryu³

et al. 2022

Jpn. J. Appl. Phys.

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Reducing the reverse recovery charge (Qrr) is effective for reducing switching loss in field plate (FP)-MOSFETs. A lifetime killer is utilized to reduce Qrr while increasing the leakage current in the off-state. Device simulation shows that a local lifetime killer on the cathode side successfully improves the trade-off between Qrr and IDSS in comparison with that of a uniform lifetime killer. A known issue of cathode lifetime killers is overshoot voltage by hard recovery. However, the overshoot voltage of FP-MOSFET decreases with a cathode lifetime killer owing to an internal snubber, which is a feature of FP-MOSFETs. An internal snubber with a large series resistance causes dynamic avalanche by both the increase of FP potential and excess carriers in high-speed operation. The cathode lifetime killer also improves dynamic avalanche by excess carriers. Consequently, the cathode lifetime killer is preferable for high-speed FP-MOSFETs.

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Section: Simulation Results Of Dynamic Avalanchementioning

confidence: 99%

Improvement of Q _rr –I _DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Kobayashi¹,

Nishiwaki²,

Goryu³

et al. 2022

Jpn. J. Appl. Phys.

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“…However, it is important to ensure that the ratio of Q GD to Q GS is controlled. If Q GS is too low then the device will be liable to parasitic turn‐on when a fast d V /d t occurs on the drain [42, 43]. This parasitic turn‐on can cause shoot‐through currents to flow in the application and can result in significant reductions in system efficiency [32].…”

Section: Silicon Performancementioning

confidence: 99%

Considerations in the design of a low‐voltage power MOSFET technology

Rutter¹

2019

IET Power Electronics

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Discrete low-voltage power metal-oxide-semiconductor field effect transistors are used in a wide variety of applications with each application relying on different aspects of device behaviour. The conflicting requirements of these applications along with constraints such as legislation, industrial base, and intellectual property have resulted in a diverse array of technologies available in the market. This study outlines the many considerations that are faced when designing a highperformance silicon power MOSFET technology contrasting the trade-offs involved as factors such as on-state resistance, switching performance, reliability, and robustness in the application are optimised. 3 Intellectual property There are ∼3000 granted US patents relating to vertical doublediffused metal-oxide-semiconductor (DMOS) devices with a trench gate (classification H01 29/7813) with the number increasing at about 300 per year. In such a fiercely competitive market, protecting intellectual property is crucial. Consideration of the

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“…The trench metal-oxide-semiconductor field effect transistor (MOSFET) has been demonstrated to be an attractive solution for various power management applications [1][2][3][4][5][6][7][8]. In today's trench MOSFET technology, the shield gate structure is widely applied to optimize the compromise relationship between on-resistance R ON and gate charge Q G , particularly gate-drain charge Q GD [9][10][11][12][13][14][15]. For the shield gate trench * Author to whom any correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

Investigation of breakdown voltage degradation in low-voltage narrow gate trench MOSFET by edge termination optimization

Wang¹,

Qiao²,

Fang³

et al. 2021

Semicond. Sci. Technol.

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In this paper, we investigate breakdown voltage degradation in a 25 V low-voltage narrow gate (NG) shield-gate trench MOSFET (NG-SGTMOS). Experiments and simulations based on Technology Computer-Aided Design (TCAD) indicate that electric field crowding and parasitic bipolar junction transistor (BJT) punch-through are responsible for the degradation of the device breakdown characteristic. To address these issues, two critical parameters, t 1 and t 2 , are optimized in the layout of the transition and termination regions of the experimental NG-SGTMOS. It is demonstrated that electric field crowding induced by excessive and non-full depletion in edge termination is successfully eliminated at t 1 = 0.6 µm. Moreover, when improving t 2 beyond 0.2 µm, the soft breakdown characteristic owing to parasitic npn-BJT punch-through can be suppressed. As a result, the breakdown voltage stability of the proposed low-voltage NG-SGTMOS is improved.

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Design criteria for shoot-through elimination in Trench Field Plate Power MOSFET

Cited by 15 publications

References 3 publications

Improvement of Q _rr –I _DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Improvement of Q _rr –I _DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Considerations in the design of a low‐voltage power MOSFET technology

Investigation of breakdown voltage degradation in low-voltage narrow gate trench MOSFET by edge termination optimization

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Design criteria for shoot-through elimination in Trench Field Plate Power MOSFET

Cited by 15 publications

References 3 publications

Improvement of Q rr –I DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Improvement of Q rr –I DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Considerations in the design of a low‐voltage power MOSFET technology

Investigation of breakdown voltage degradation in low-voltage narrow gate trench MOSFET by edge termination optimization

Contact Info

Product

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Improvement of Q _rr –I _DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Improvement of Q _rr –I _DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side