Investigation of breakdown voltage degradation in low-voltage narrow gate trench MOSFET by edge termination optimization

Abstract

In this paper, we investigate breakdown voltage degradation in a 25 V low-voltage narrow gate (NG) shield-gate trench MOSFET (NG-SGTMOS). Experiments and simulations based on Technology Computer-Aided Design (TCAD) indicate that electric field crowding and parasitic bipolar junction transistor (BJT) punch-through are responsible for the degradation of the device breakdown characteristic. To address these issues, two critical parameters, t 1 and t 2 , are optimized in the layout of the transition and termination regions of the experimental NG-SGTMOS. It is demonstrated that electric field crowding induced by excessive and non-full depletion in edge termination is successfully eliminated at t 1 = 0.6 µm. Moreover, when improving t 2 beyond 0.2 µm, the soft breakdown characteristic owing to parasitic npn-BJT punch-through can be suppressed. As a result, the breakdown voltage stability of the proposed low-voltage NG-SGTMOS is improved.

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“…However, an exceptionally thin base region or a base region characterize by low doping concentration may induce punch-through effect. [16] The effect of the thickness and doping of the base region on anode I−V characteristics current gain had been studied. the base region.…”