Design Considerations Towards Zero-Variability Resistive RAMs in HRS State

Abstract

Resistive RAM (RAM) intrinsic variability is widely recognized as a major hurdle for widespread adoption of the technology. Moreover, the deeper we go into the High Resistance State (HRS), the higher the variability. In this context, this paper proposes circuit level design strategies to mitigate HRS variability. During the RESET operation, the programming current is strictly controlled while the voltage across the RRAM cell is regulated. From a design standpoint, a write termination circuit is used to constantly sense the programming current and stop the RESET pulse when the preferred RESET current is reached. The write termination is combined with a voltage regulator which provides a strict control of the RESET voltage. The paper first reviews the RRAM variability phenomenon. Then, an optimized programming scheme is developed to control the HRS state to approach zero-variability. Compared to the classical fixed-pulse programming scheme, variability is reduced by 99%.

Oxide-based Resistive RAM Analog Synaptic Behavior Assessment for Neuromemristive systems

“…Conversely, if during an RST operation too many ions are displaced, the voltage needed to induce an efficient SET operation in the next programming cycle may not be sufficient, leading the device to be stuck at HRS for several cycles [47,48]. To mitigate soft error impact on memristive networks, it is necessary to design specific circuits able to monitor the effectiveness of each RST/SET operation [18,49]. Also, it has a been reported at the memory array level that during consecutive RST/SET operations, write disturb can occur and impact the performance of the memory cells.…”

Design and optimization of asynchronous FIFO based on Verilog HDL

“…Random Access Memory, or RAM, is a module used to store incoming data. Because the module can be read or written at any time, it is often used as a temporary storage medium for the operating system or other running programs, similar to mobile storage on PC [4]. The RAM module was shown in figure 3.…”

Analysis of Conductance Variability in RRAM for Accurate Neuromorphic Computing

“…An alternative way to mitigate conductance fluctuations issues at the NN level is the mapping-aware biased training methodology [7] which consists in identifying RRAM conductance states inherently more immune to variation (favorable states). Then, a mapping-aware training technique is adopted where important weights are directly get mapped to such favorable states [8]. The mapping-aware training considers the inherent non-idealities of RRAM devices, such as variations in the conductance levels in the first place [8].…”

“…Then, a mapping-aware training technique is adopted where important weights are directly get mapped to such favorable states [8]. The mapping-aware training considers the inherent non-idealities of RRAM devices, such as variations in the conductance levels in the first place [8]. Therefore, detecting devices suffering from variability issues is a crucial step before considering a mapping-aware training methodology practical implementation.…”