Design and optimization of asynchronous FIFO based on Verilog HDL

Abstract

SoC system is a new chip design scheme, which can integrate a large number of functions in the same chip, so it has high requirements for asynchronous data transmission between different modules. Asynchronous FIFO is an efficient and reliable data transmission mode, which is often used as a data matcher in SoC system. This paper, through the modular design, layer by layer construction method, designs a asynchronous FIFO, and for the common problems to optimize, makes its performance more reliable. And according to the simulation results, it can be judged that this design can effectively and reliably carry out asynchronous data transmission.